RECONFIGURABLE MEMORY INTERFACE CIRCUIT TO SUPPORT A BUILT-IN MEMORY SCAN CHAIN
    1.
    发明申请
    RECONFIGURABLE MEMORY INTERFACE CIRCUIT TO SUPPORT A BUILT-IN MEMORY SCAN CHAIN 有权
    可重构存储器接口电路支持内置存储器扫描链

    公开(公告)号:US20150058686A1

    公开(公告)日:2015-02-26

    申请号:US13975277

    申请日:2013-08-23

    Abstract: A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.

    Abstract translation: 提供了在功能模式和ATPG扫描模式下操作装置的方法以及用于功能模式和ATPG扫描模式的装置。 该装置包括一组锁存器,其包括第一锁存器和第二锁存器。 第一个锁存器作为主锁存器操作,第二个锁存器在功能模式下作为主锁存器运行。 第一个锁存器作为触发器的主锁存器操作,第二个锁存器在ATPG扫描模式下作为触发器的从锁存器操作。 在一种配置中,该装置包括至少包括第一和第二锁存器的多个锁存器,每个锁存器的输出耦合到数字电路,该装置包括多个功能输入,并且每个功能输入是 输入到数字电路。

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