公开(公告)号：US10191850B2

公开(公告)日：2019-01-29

申请号：US15086817

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/08 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/04 ,  G06F12/084 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0862

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

公开(公告)号：US10042771B2

公开(公告)日：2018-08-07

申请号：US15718449

申请日：2017-09-28

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/04 ,  G06F12/12 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0862

CPC classification number: G06F12/0875 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

公开(公告)号：US10146693B2

公开(公告)日：2018-12-04

申请号：US15718449

申请日：2017-09-28

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/04 ,  G06F12/12 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0862

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

公开(公告)号：US20180018268A1

公开(公告)日：2018-01-18

申请号：US15718449

申请日：2017-09-28

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/04 ,  G06F12/12

CPC classification number: G06F12/0875 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

公开(公告)号：US20170286308A1

公开(公告)日：2017-10-05

申请号：US15086817

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.