公开(公告)号：US20200073836A1

公开(公告)日：2020-03-05

申请号：US16115388

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Lior Amarilio ,  Mark Gakman

IPC: G06F13/362 ,  G06F13/42 ,  G06F1/32 ,  G06F1/10

Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

公开(公告)号：US10678723B2

公开(公告)日：2020-06-09

申请号：US16134559

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Lior Amarilio ,  Mark Gakman

IPC: G06F13/24 ,  G06F13/362 ,  G06F13/42

Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over an I3C serial bus. A method performed at a slave device includes driving a data line of the I3C serial bus from a high state to a low state before a first clock pulse is received from a clock line of the I3C serial bus after a start condition has been provided on the I3C serial bus, where driving the data line from the high state to the low state produces an initial pulse on the data line, transmitting one or more additional pulses on the data line before the first clock pulse is transmitted on the clock line, and driving the data line low until a rising edge of the first clock pulse is detected on the clock line after each of the plurality of additional pulses has been successfully transmitted on the data line.

公开(公告)号：US10725949B2

公开(公告)日：2020-07-28

申请号：US16115388

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Lior Amarilio ,  Mark Gakman

IPC: G06F13/362 ,  G06F13/42 ,  G06F1/32 ,  G06F1/10 ,  G06F1/3296 ,  G06F1/3293 ,  G06F1/3287

Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.