公开(公告)号：US20170338940A1

公开(公告)日：2017-11-23

申请号：US15270444

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Marco ZANUSO ,  Mohammad ELBADRY ,  Tsai-Pi HUNG ,  Ravi SRIDHARA ,  Francesco GATTA ,  Jingcheng ZHUANG

IPC: H04L7/033 ,  H04L5/14 ,  H04L29/06 ,  H04W84/04

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.