公开(公告)号：US20210351696A1

公开(公告)日：2021-11-11

申请号：US17443093

申请日：2021-07-20

申请人： QUALCOMM Incorporated

发明人： Yung-Chung LO ,  Gang ZHANG ,  Yiping HAN ,  Frederic BOSSU ,  Tsai-Pi HUNG ,  Jae-Hong CHANG

IPC分类号： H02M3/156 ,  H02M1/00 ,  G05F1/575

摘要： A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.

公开(公告)号：US20170338940A1

公开(公告)日：2017-11-23

申请号：US15270444

申请日：2016-09-20

申请人： QUALCOMM Incorporated

发明人： Marco ZANUSO ,  Mohammad ELBADRY ,  Tsai-Pi HUNG ,  Ravi SRIDHARA ,  Francesco GATTA ,  Jingcheng ZHUANG

IPC分类号： H04L7/033 ,  H04L5/14 ,  H04L29/06 ,  H04W84/04

CPC分类号： H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

摘要： A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

公开(公告)号：US20150349622A1

公开(公告)日：2015-12-03

申请号：US14630506

申请日：2015-02-24

申请人： QUALCOMM Incorporated

发明人： Yung-Chung LO ,  Gang ZHANG ,  Yiping HAN ,  Frederic BOSSU ,  Tsai-Pi HUNG ,  Jae-Hong CHANG

IPC分类号： H02M1/00 ,  H02M3/156

CPC分类号： H02M3/156 ,  G05F1/575 ,  H02M1/00 ,  H02M2001/0077

摘要： A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

摘要翻译： 提供了一种方法，装置和计算机程序产品。 该装置可以是调节器电路。 调节器电路包括第一电压调节器，用于调节到第一电压调节器的第一输入电压，第一电压调节器包括P型金属氧化物半导体（PMOS）和第二电压调节器，以将第二输入电压调节到 第二电压调节器，第二电压调节器包括N型金属氧化物半导体（NMOS）。 在一方面，第一电压调节器耦合到第二电压调节器。

公开(公告)号：US20170310458A1

公开(公告)日：2017-10-26

申请号：US15269320

申请日：2016-09-19

申请人： QUALCOMM Incorporated

发明人： Marco ZANUSO ,  Giovanni MARUCCI ,  Tsai-Pi HUNG ,  Francesco GATTA ,  Bo SUN

IPC分类号： H04L7/033 ,  H04W72/04 ,  H04B1/40

CPC分类号： H04L7/0331 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/06 ,  H04B1/40 ,  H04B1/713 ,  H04B2201/71353 ,  H04W72/0453

摘要： A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

公开(公告)号：US20150349712A1

公开(公告)日：2015-12-03

申请号：US14489444

申请日：2014-09-17

申请人： QUALCOMM Incorporated

发明人： Tsai-Pi HUNG ,  Gang ZHANG ,  Jae-Hong CHANG ,  Yung-Chung LO ,  Jianjun YU ,  Yuehai JIN

IPC分类号： H03B5/12

CPC分类号： H03B5/1265 ,  H03B5/1212 ,  H03B5/1243

摘要： Aspects of a reconfigurable varactor array for providing a capacitance to control an output frequency of a voltage-controlled oscillator are provided. The reconfigurable varactor array can be configured to provide a configurable capacitance. The reconfigurable varactor array can include a plurality of varactor cells connected in parallel. The reconfigurable varactor array can also include a control circuit configured to receive a control signal to select the configurable capacitance from the reconfigurable varactor array. The control circuit can include a plurality of switch groups. Each switch group can be separately connected to one varactor cell in the reconfigurable varactor array. The control signal from the control circuit can control operation of each switch group.

摘要翻译： 提供了用于提供电容以控制压控振荡器的输出频率的可重构变容二极管阵列的方面。 可配置变容二极管阵列可以配置为提供可配置的电容。 可重构变容二极管阵列可以包括并联连接的多个变容二极管单元。 可重构变容二极管阵列还可以包括控制电路，其被配置为接收控制信号以从可重构变容二极管阵列中选择可配置电容。 控制电路可以包括多个开关组。 每个开关组可以单独连接到可重新配置的变容二极管阵列中的一个变容二极管单元。 来自控制电路的控制信号可以控制每个开关组的操作。