公开(公告)号：US09152595B2

公开(公告)日：2015-10-06

申请号：US13654653

申请日：2012-10-18

Applicant: QUALCOMM Incorporated

Inventor： Jaya Prakash Subramaniam Ganasan ,  Mark Michael Schaffer ,  Prudhvi N. Nooney ,  Perry Willmann Remaklus, Jr.

IPC: G06F1/32 ,  G06F13/40 ,  G06F15/173 ,  G06F13/368

CPC classification number: G06F13/4027 ,  G06F1/3287 ,  G06F13/368 ,  G06F13/4004 ,  G06F15/17375 ,  Y02D10/14 ,  Y02D10/151

Abstract: Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.

Abstract translation: 公开了基于处理器的系统混合环形总线互连以及相关设备，系统和方法。 在一个实施例中，提供了基于处理器的系统混合环形总线互连。 基于处理器的系统混合环形总线互连包括多个环形总线，每个环形总线具有总线宽度并且被配置为从请求者设备接收总线事务消息。 基于处理器的系统混合环形总线互连还包括耦合到环形总线的环形间路由器。 环形路由器被配置为基于请求者设备的带宽需求来动态地指导环形总线中的总线事务消息。 因此，由于更简单的开关配置，功率消耗比交叉开关互连更少。 此外，环形路由器允许提供可以基于带宽需求被动态地激活和去激活的多个环形总线。 当不需要基于处理器的系统混合环形总线互连的全带宽要求时，这提供了功率的保护。

公开(公告)号：US11016899B2

公开(公告)日：2021-05-25

申请号：US16403701

申请日：2019-05-06

Applicant: QUALCOMM Incorporated

Inventor： Nikhil Narendradev Sharma ,  Eric Francis Robinson ,  Garrett Michael Drapala ,  Perry Willmann Remaklus, Jr. ,  Joseph Gerald McDonald ,  Thomas Philip Speier

IPC: G06F13/00 ,  G06F12/0862

Abstract: Selective honoring of speculative memory-prefetch requests based on bandwidth constraint of a memory access path component(s) in a processor-based system. To reduce memory access latency, a CPU includes a request size in a memory read request of requested data to be read from memory and a request mode of the requested data as required or preferred. A memory access path component includes a memory read honor circuit configured to receive the memory read request and consult the request size and request mode of requested data in the memory read request. If the selective prefetch data honor circuit determines that bandwidth of the memory system is less than a defined bandwidth constraint threshold, then the memory read request is forwarded to be fulfilled, otherwise, the memory read request is downgraded to only include any requested required data.

公开(公告)号：US10191682B2

公开(公告)日：2019-01-29

申请号：US15259686

申请日：2016-09-08

Applicant: QUALCOMM Incorporated

Inventor： Mattheus Cornelius Antonius Adrianus Heddes ,  Perry Willmann Remaklus, Jr.

IPC: H03M7/00 ,  H03M7/34 ,  H03M7/30 ,  G06F3/06 ,  G06F12/0897 ,  G06F13/16

Abstract: Providing efficient lossless compression for small data blocks in processor-based systems is provided. In one aspect, a method comprises receiving a plurality of input words. Each mask of a plurality of masks is applied to each unassigned input word to generate a corresponding plurality of patterns. For each mask, if a most frequently occurring pattern exists among the plurality of patterns, the most frequently occurring pattern and an uncompressed data portion of each unassigned input word are stored in association with a prefix associated with the mask. The prefix is also assigned to each unassigned input word corresponding to the most frequently occurring pattern. A compressed output block is generated, comprising prefixes assigned to the plurality of input words, the most frequently occurring patterns associated with the assigned prefixes, and uncompressed data portions corresponding to one or more input words of the plurality of input words.