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公开(公告)号:US09858217B1
公开(公告)日:2018-01-02
申请号:US15197524
申请日:2016-06-29
Applicant: QUALCOMM Incorporated
Inventor: Percy Tehmul Marfatia , Rajagopal Narayanan , Shih-Hsin Jason Hu , Nan Chen
CPC classification number: G06F13/1689 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F1/3296 , G11C5/14 , G11C7/04 , G11C7/1072 , G11C7/22 , G11C7/227 , G11C11/417
Abstract: An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit. A method is presented. The method includes at least operating a timing circuit to emulate a first operation of the memory, activating a second operation of the memory based on the emulating the first operation of the memory, emulating, by a sensor, a portion of the timing circuit. Another apparatus is presented. The apparatus includes at least a memory, a timing circuit, and means for tracking a performance of the memory based on the timing circuit tracking a memory operation.
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公开(公告)号:US10326431B1
公开(公告)日:2019-06-18
申请号:US15941055
申请日:2018-03-30
Applicant: QUALCOMM Incorporated
Inventor: Pratik Rajeshbhai Patel , Percy Tehmul Marfatia , Rajagopal Narayanan
IPC: H03K19/082 , H03K3/356 , H03K19/0185
Abstract: A novel clock level-shifter to reduce duty-cycle distortion across wide input-output voltage operating range is disclosed. In some implementations, a level shifter includes an input stage coupled to a first power supply to receive an input signal, an output stage coupled to a second power supply to generate an output signal, and a first switch coupled directly between the output stage and the second power supply, wherein the input signal turns on or off the first switch. In some implementations, the first switch has a gate, a source, and a drain, the source being coupled to the second power supply, the drain being coupled to the output stage, and the gate being driven directly by the input signal.
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