公开(公告)号：US20240202140A1

公开(公告)日：2024-06-20

申请号：US18081396

申请日：2022-12-14

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Rajendra Varma PUSAPATI ,  Ravindranath DODDI ,  Yogananda Rao CHILLARIGA

IPC: G06F13/12

CPC classification number: G06F13/126 ,  G06F2213/0026

Abstract: Aspects relate to lane failure recovery for a data link having multiple lanes labeled in a contiguous sequence. In one aspect, a failure of a failed lane of the data link is detected. Working lanes of the data link are then detected. A set of contiguous working lanes of the data link are selected, and an operational link as including the selected set of contiguous working lanes is defined. A start address of the operational link is identified and stored in a configuration register. Data traffic is transmitted on the operational link.

公开(公告)号：US20250091436A1

公开(公告)日：2025-03-20

申请号：US18467128

申请日：2023-09-14

Applicant: QUALCOMM Incorporated

Inventor： Vinod Kumar ENAPAKURTHI ,  Raviteja VEERELLA ,  Ramakrishna PALLALA ,  Rajendra Varma PUSAPATI

IPC: B60K35/00

Abstract: Various embodiments include methods and vehicle processing systems for repositioning safety critical information from a primary cluster display to another vehicle display in the event that the primary cluster display malfunctions or otherwise cannot display that information. Embodiments may include recognizing when there is a malfunction in the primary cluster display, and operations that enable safety critical information to be rendered on a different display, such as a display of a vehicle infotainment system.

公开(公告)号：US20240427710A1

公开(公告)日：2024-12-26

申请号：US18339904

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Ravindranath DODDI ,  Rajendra Varma PUSAPATI ,  Sonali JABREVA

IPC: G06F13/16

Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link configuration by a computing device. Embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, and selecting, by the PCIe device, a PCIe link width of one lane for configuring the PCIe link. Embodiments may include selecting a PCIe link speed level lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold for a first PCIe link configuration mode. Embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Embodiments may include increasing the PCIe link width in response to a requested bandwidth exceeding a configuration bandwidth of the PCIe link.

公开(公告)号：US20240378166A1

公开(公告)日：2024-11-14

申请号：US18314676

申请日：2023-05-09

Applicant: QUALCOMM INCORPORATED

Inventor： Madhu Yashwanth BOENAPALLI ,  Kaustub Naidu PAILA RAM ,  Sravani DEVINENI ,  Sai Praneeth SREERAM ,  Vinod KUMAR KURUMA ,  Rajendra Varma PUSAPATI ,  Surendra PARAVADA

IPC: G06F13/42

Abstract: A Peripheral Component Interconnect Express (PCIe) system is configured to determine when the frequency of link speed switching needed to service incoming and upcoming client requests is too high. The system is also configured to determine a modest link speed to be used to service incoming and upcoming client requests in cases where the link speed switching that will be needed is too high and causes the incoming and upcoming client requests to be serviced at the modest link speed instead of at the link speeds associated with the predefined BWs of the clients. By doing this when the frequency of link speed switching needed is too high, the PCIe system achieves better throughput while also reducing power consumption.