公开(公告)号：US20240345762A1

公开(公告)日：2024-10-17

申请号：US18298484

申请日：2023-04-11

Applicant: QUALCOMM Incorporated

Inventor： Sravani DEVINENI ,  Sai Praneeth SREERAM ,  Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for updating logical-to-physical (L2P) address mapping tables. Various embodiments may include enabling a device control mode (DCM) of host performance booster (HPB) based on a flush of a writebooster buffer to a normal storage of a UFS device of the UFS system, and updating an L2P address mapping table at a host device of the UFS system while DCM is enabled based on the flush of the writebooster buffer to the normal storage. Some embodiments may include generating a signal having an indicator of a UFS protocol information unit configured to indicate a change in an HPB mode at the UFS device based on the flush of the writebooster buffer to the normal storage, and sending the signal from the UFS device to the host device.

公开(公告)号：US20240184711A1

公开(公告)日：2024-06-06

申请号：US18061451

申请日：2022-12-03

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Sai Praneeth SREERAM

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/1016

Abstract: Methods that may be performed by a host controller of a computing device for host performance booster (HPB) mode management. Embodiments may include enabling an HPB mode based on availability of the host controller and availability of a memory device controller. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a device control mode in response to an operating state of the host controller being busy and an operating state of the memory device controller being available. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a host control mode in response to the operating state of the host controller being available and the operating state of the memory device controller being busy.

公开(公告)号：US20200348884A1

公开(公告)日：2020-11-05

申请号：US16400468

申请日：2019-05-01

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Sai Praneeth SREERAM ,  Surendra PARAVADA ,  Venu Madhav MOKKAPATI

IPC: G06F3/06

Abstract: In some aspects, the present disclosure provides a method for managing data communication rates of a memory device. The method includes receiving an input/output (I/O) operation to be performed by the memory device, detecting a temperature of the memory device, and determining whether the detected temperature satisfies a threshold condition. The threshold condition is satisfied if the detected temperature is above a first temperature threshold or below a second temperature threshold. If the threshold condition is satisfied, selecting a gear from a plurality of gears based on a ranking of the plurality of gears at the detected temperature, wherein each gear of the plurality of gears correspond to a respective one of a plurality of data rates used by the memory device for performing I/O operations, and serving, to the memory device, the I/O operation with an indication to perform the I/O operation using the selected gear.

公开(公告)号：US20240348437A1

公开(公告)日：2024-10-17

申请号：US18301305

申请日：2023-04-17

Applicant: QUALCOMM Incorporated

Inventor： Sridhar ANUMALA ,  Bharani BHUVANAGIRI ,  Nishanth KUMAR ,  Dhananjayan ATHIYAPPAN ,  Madhu Yashwanth BOENAPALLI

IPC: H04L9/08

CPC classification number: H04L9/088 ,  H04L9/0819

Abstract: Various embodiments include methods implemented in a processor for management of cryptographic keys of an integrated cryptographic engine. Embodiments may include detecting a cryptographic key access control event, determining whether the cryptographic key access control event is for disabling cryptographic key access at a cryptographic key memory of the integrated cryptographic engine, disabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is for disabling cryptographic key access at the cryptographic key memory, and maintaining one or more cryptographic keys at the cryptographic key memory for which cryptographic key access is disabled. Embodiments may further include enabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is not for disabling cryptographic key access at the cryptographic key memory.

公开(公告)号：US20200084130A1

公开(公告)日：2020-03-12

申请号：US16124507

申请日：2018-09-07

Applicant: QUALCOMM Incorporated

Inventor： Venu Madhav MOKKAPATI ,  Gurudutt NARASIMHA ,  Uday Kumar ARAVA ,  Madhu Yashwanth BOENAPALLI

IPC: H04L12/26 ,  H04L5/00 ,  H04L29/08 ,  H04W76/10

Abstract: Systems, methods, and apparatus for rewriting or adjusting a TCP timestamp value are described. The methodology includes determining network conditions of a wireless network, and establishing a transmission control protocol (TCP) connection between a first communication device and a second communication device via the wireless network. The timestamp value within a TCP packet to be transmitted, such as as a TCP SYN ACK packet in a 3-way handshake, is adjusted with the use of a timestamp adjusting circuitry or hardware, where the adjustment is based on the determined network conditions. By adjusting the timestamp of a TCP packet prior to transmission and based on network conditions, unnecessary retransmissions are reduced. Additionally, the use of timestamp adjusting hardware allows for more efficient timestamp adjustment by offloading processor computations.

公开(公告)号：US20190179540A1

公开(公告)日：2019-06-13

申请号：US15838348

申请日：2017-12-11

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Hyunsuk SHIN ,  Venu Madhav MOKKAPATI

IPC: G06F3/06

Abstract: In a conventional system with an embedded UFS and an external UFS card are connected to a UFS host, the UFS host is only able to transfer data to the embedded UFS or to the an external UFS card, but not to both at the same time. To address this issue, it is proposed to provide a host that is capable of concurrently transferring data to multiple storage devices.

公开(公告)号：US20240419613A1

公开(公告)日：2024-12-19

申请号：US18337235

申请日：2023-06-19

Applicant: QUALCOMM INCORPORATED

Inventor： Madhu Yashwanth BOENAPALLI ,  Ravindranath DODDI ,  Vinod Kumar KURUMA ,  Surendra PARAVADA ,  Sai Praneeth SREERAM

IPC: G06F13/16

Abstract: A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced power consumption and latency. When the link transitions from an active functional state in which the link has a first configuration of N active lanes to a power-saving state, the number of active lanes is collapsed such that M of the N lanes are maintained in an active power-saving state and P of the N lanes are maintained in an electrically idle state, where M, N and P are positive integers and N>P>M. The reduction in lane width reduces power consumption. Bit values specifying the current link configuration can be saved in a control register and read and compared to bit values contained in a link control register before transitioning back to the active functional state. If the bit values match, the active functional state is resumed directly from the recovery state, thereby reducing latency.

公开(公告)号：US20240160576A1

公开(公告)日：2024-05-16

申请号：US18054249

申请日：2022-11-10

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Surendra PARAVADA ,  Sai Praneeth SREERAM

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/1028 ,  G06F2212/655

Abstract: Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.

公开(公告)号：US20190340421A1

公开(公告)日：2019-11-07

申请号：US15967866

申请日：2018-05-01

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Venu Madhav MOKKAPATI ,  Surendra PARAVADA

IPC: G06K9/00 ,  H04N5/235 ,  G06T7/136

Abstract: Certain aspects of the present disclosure provide techniques for performing face recognition in low light conditions using an electronic device. One aspect provides a method including determining if a brightness level within a viewing area of the electronic device satisfies a threshold. The method includes increasing a luminance output of the electronic device from a first luminance level to a second luminance level when the brightness level does not satisfy the threshold. The method includes capturing an image at the second luminance level when the brightness level does not satisfy the threshold. The method includes capturing the image at the first luminance level when the brightness level satisfies the threshold. The method includes detecting a face in the image. The method includes determining if the face corresponds to an authorized user. The method includes unlocking the electronic device when the face corresponds to an authorized user.

公开(公告)号：US20190303313A1

公开(公告)日：2019-10-03

申请号：US15937814

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Madhu Yashwanth BOENAPALLI ,  Venu Madhav MOKKAPATI ,  Surendra PARAVADA

IPC: G06F13/16 ,  G06F13/42

Abstract: In a conventional system with a UFS storage device connected to a UFS host over one or more lanes, the lanes can support different transmission speeds, referred to as gears. The UFS host shifts lanes and gears based on the type of request it receives. When the requests arrive in random order of gear requirements, the frequent shifting of the lanes and gears causes significant power consumption. To address this issue, it is proposed to implement a queue-based shifting in which arriving requests may be queued based on their gear requirements. When a queue is selected, multiple requests in the selected queue, which are all of same or similar gear requirement, can be served. This can reduce the frequency of gear shifting, and hence reduce power consumption.