公开(公告)号：US20180253129A1

公开(公告)日：2018-09-06

申请号：US15449836

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： Harmander Singh ,  Sebastien Weyland ,  Suresh Kumar Venkumahanti

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G11C5/148 ,  G11C16/20 ,  G11C16/30 ,  G11C29/021 ,  G11C29/028

Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.

公开(公告)号：US10353447B2

公开(公告)日：2019-07-16

申请号：US15449836

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： Harmander Singh ,  Sebastien Weyland ,  Suresh Kumar Venkumahanti

IPC: G06F1/26 ,  G11C5/14 ,  G11C16/20 ,  G11C16/30 ,  G11C29/02

Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.