公开(公告)号：US20180253129A1

公开(公告)日：2018-09-06

申请号：US15449836

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： Harmander Singh ,  Sebastien Weyland ,  Suresh Kumar Venkumahanti

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G11C5/148 ,  G11C16/20 ,  G11C16/30 ,  G11C29/021 ,  G11C29/028

Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.

公开(公告)号：US09299419B1

公开(公告)日：2016-03-29

申请号：US14611482

申请日：2015-02-02

Applicant: QUALCOMM Incorporated

Inventor： Harmander Singh ,  Milena Vratonjic ,  Ian David O'Donnell ,  Kenneth Gainey

IPC: G11C5/14 ,  G11C11/00 ,  G11C11/417 ,  G11C5/00

CPC classification number: G11C11/417 ,  G11C5/005 ,  G11C5/14 ,  G11C5/147

Abstract: Systems and methods for optimizing a memory rail voltage are disclosed. The system may comprise a plurality of sensor cells, each sensor cell comprising at least one bitcell replica having a predefined data retention voltage higher than a data retention voltage of a similar memory bit cell. The sensor cells may be configured to provide an output based on a sensor rail voltage higher than the predefined data retention voltage. The system may further comprise a controller operably coupled to a power management circuit and configured to adjust the memory rail and the sensor rail voltages. The controller may be further configured to compare an expected value to the sensor indication. The controller may decrease the sensor rail voltage and the memory rail voltage based on the indication until a sensor indicates a bitcell replica has failed, indicating an optimum memory rail voltage has been reached.

Abstract translation: 公开了用于优化存储器轨电压的系统和方法。 该系统可以包括多个传感器单元，每个传感器单元包括至少一个比特单元复制品，其具有高于类似存储器位单元的数据保持电压的预定数据保持电压。 传感器单元可以被配置为基于高于预定数据保持电压的传感器轨道电压来提供输出。 系统还可以包括可操作地耦合到功率管理电路并被配置为调整存储器轨和传感器轨电压的控制器。 控制器还可以被配置为将预期值与传感器指示进行比较。 控制器可以基于指示降低传感器轨电压和存储器轨电压，直到传感器指示位单元副本已经失败，表明已经达到最佳存储器轨电压。

公开(公告)号：US10331195B2

公开(公告)日：2019-06-25

申请号：US15468039

申请日：2017-03-23

Applicant: QUALCOMM Incorporated

Inventor： Milena Vratonjic ,  Harmander Singh ,  Gautam Kumar ,  Mohamed Roumi ,  Kenneth Marvin Gainey ,  Ashish Bajaj

IPC: G06F1/32 ,  G06F1/3225 ,  G06F1/324 ,  G06F13/16

Abstract: In some aspects, a method for adjusting an operating frequency of a memory controller is provided, wherein a graphics processing unit (GPU) accesses a memory via the memory controller. The method includes monitoring activity of the GPU to determine an active time of the GPU, comparing the determined active time with an active threshold, and, if the determined active time is greater than the active threshold, increasing the operating frequency of the memory controller.

公开(公告)号：US20170351316A1

公开(公告)日：2017-12-07

申请号：US15468039

申请日：2017-03-23

Applicant: QUALCOMM Incorporated

Inventor： Milena Vratonjic ,  Harmander Singh ,  Gautam Kumar ,  Mohamed Roumi ,  Kenneth Marvin Gainey ,  Ashish Bajaj

IPC: G06F1/32 ,  G06F13/16

CPC classification number: G06F1/324 ,  G06F1/3225 ,  G06F13/1668 ,  G06F13/1689 ,  Y02D10/126

Abstract: In some aspects, a method for adjusting an operating frequency of a memory controller is provided, wherein a graphics processing unit (GPU) accesses a memory via the memory controller. The method includes monitoring activity of the GPU to determine an active time of the GPU, comparing the determined active time with an active threshold, and, if the determined active time is greater than the active threshold, increasing the operating frequency of the memory controller.

公开(公告)号：US10353447B2

公开(公告)日：2019-07-16

申请号：US15449836

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： Harmander Singh ,  Sebastien Weyland ,  Suresh Kumar Venkumahanti

IPC: G06F1/26 ,  G11C5/14 ,  G11C16/20 ,  G11C16/30 ,  G11C29/02

Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.