公开(公告)号：US09496873B2

公开(公告)日：2016-11-15

申请号：US14451079

申请日：2014-08-04

Applicant: QUALCOMM Incorporated

Inventor： Shengyuan Li ,  Iulian Mirea

IPC: H03K19/094 ,  H03K19/0185 ,  H03K3/356 ,  H03K5/24 ,  H03K19/017

CPC classification number: H03K19/0185 ,  H03K3/35613 ,  H03K5/2481 ,  H03K19/01721 ,  H03K19/018514

Abstract: In one embodiment, a method for increasing speed of a differential input pair. The method comprises applying a first boost current to a first input of the differential input pair during a transition of a first signal applied to the first input; storing the first boost current; ending the application of the first boost current in response to the stored first boost current exceeding a first threshold; applying a second boost current to a second input of the differential input pair during a transition of a second signal applied to the second input; storing the second boost current; and ending the application of the second boost current in response to the stored second boost current exceeding a second threshold.

Abstract translation: 在一个实施例中，一种用于增加差分输入对的速度的方法。 该方法包括：在施加到第一输入端的第一信号的转变期间，将第一升压电流施加到差分输入对的第一输入; 存储第一升压电流; 响应于所存储的第一升压电流超过第一阈值，结束施加第一升压电流; 在施加到所述第二输入的第二信号的转变期间，将第二升压电流施加到所述差分输入对的第二输入; 存储第二升压电流; 以及响应于所存储的超过第二阈值的第二升压电流而结束施加第二升压电流。

公开(公告)号：US20160036444A1

公开(公告)日：2016-02-04

申请号：US14449393

申请日：2014-08-01

Applicant: QUALCOMM Incorporated

Inventor： Shengyuan Li

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K19/017545 ,  H03K3/356104 ,  H03K19/0005 ,  H03K19/018528

Abstract: In one embodiment, a circuit comprises a phase interpolator that converts a single-ended input to a pair of symmetric differential signals within a first voltage domain. The circuit further comprises a comparator that converts the symmetric differential signals into single-ended output in a second different voltage domain. In one embodiment, the single ended output of the comparator is configured to be coupled to drive a switching driver in a switching regulator. In one embodiment, the interpolator comprises a first inverter, a second inverter, and a third inverter connected in series. The interpolator further comprises a first resistor and a second resistor connected in series. The second inverter provides a first output signal. Outputs of the first inverter and the third inverter are connected by the series connected resistors. A node between the resistors provides a second output signal. The first and second output signals are inverted and symmetric.

Abstract translation: 在一个实施例中，电路包括相位插值器，其将单端输入转换成第一电压域内的一对对称差分信号。 电路还包括比较器，其将对称差分信号转换成第二不同电压域中的单端输出。 在一个实施例中，比较器的单端输出被配置为耦合以驱动开关稳压器中的开关驱动器。 在一个实施例中，内插器包括串联连接的第一反相器，第二反相器和第三反相器。 内插器还包括串联连接的第一电阻器和第二电阻器。 第二个反相器提供第一个输出信号。 第一个反相器和第三个反相器的输出通过串联电阻连接。 电阻之间的节点提供第二个输出信号。 第一和第二输出信号是反相和对称的。

公开(公告)号：US20160036443A1

公开(公告)日：2016-02-04

申请号：US14451079

申请日：2014-08-04

Applicant: QUALCOMM Incorporated

Inventor： Shengyuan Li ,  Iulian Mirea

IPC: H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/0185 ,  H03K3/35613 ,  H03K5/2481 ,  H03K19/01721 ,  H03K19/018514

Abstract: In one embodiment, a method for increasing speed of a differential input pair, The method comprises applying a first boost current to a first input of the differential input pair during a transition of a first signal applied to the first input; storing the first boost current; ending the application of the first boost current in response to the stored first boost current exceeding a first threshold; applying a second boost current to a second input of the differential input pair during a transition of a second signal applied to the second input; storing the second boost current; and ending the application of the second boost current in response to the stored second boost current exceeding a second threshold.

Abstract translation: 在一个实施例中，一种用于增加差分输入对的速度的方法。所述方法包括：在施加到第一输入的第一信号的转变期间，将第一升压电流施加到差分输入对的第一输入; 存储第一升压电流; 响应于所存储的第一升压电流超过第一阈值，结束施加第一升压电流; 在施加到所述第二输入的第二信号的转变期间，将第二升压电流施加到所述差分输入对的第二输入; 存储第二升压电流; 以及响应于所存储的超过第二阈值的第二升压电流而结束施加第二升压电流。

公开(公告)号：US20160036313A1

公开(公告)日：2016-02-04

申请号：US14451249

申请日：2014-08-04

Applicant: QUALCOMM Incorporated

Inventor： Shengyuan Li ,  Chunlei Shi ,  Loc Nguyen

IPC: H02M1/00 ,  H02M3/158

CPC classification number: H02M1/00 ,  H02M1/34 ,  H02M3/158 ,  H02M2001/0003 ,  H02M2001/344

Abstract: The present disclosure includes programmable snubber circuits and methods. In one embodiment, a circuit is configured between first and second power supply terminals. A programmable snubber circuit may be configured between the first and second power supplies to reduce ringing on the power supplies. In one embodiment, the circuit is a switching regulator and the power supply terminals are internal power supply terminals. The snubber circuit may be programmed to reduce ringing caused by switching currents through parasitic inductances in a package.

Abstract translation: 本公开包括可编程缓冲电路和方法。 在一个实施例中，电路被配置在第一和第二电源端子之间。 可编程缓冲电路可以配置在第一和第二电源之间，以减少电源上的振铃。 在一个实施例中，电路是开关调节器，电源端子是内部电源端子。 缓冲电路可以被编程为减少由开关电流通过封装中的寄生电感引起的振铃。

公开(公告)号：US09236789B1

公开(公告)日：2016-01-12

申请号：US14451249

申请日：2014-08-04

Applicant: QUALCOMM Incorporated

Inventor： Shengyuan Li ,  Chunlei Shi ,  Loc Nguyen

IPC: H02M1/00 ,  H02M3/158 ,  H02J3/24

CPC classification number: H02M1/00 ,  H02M1/34 ,  H02M3/158 ,  H02M2001/0003 ,  H02M2001/344

Abstract: The present disclosure includes programmable snubber circuits and methods. In one embodiment, a circuit is configured between first and second power supply terminals. A programmable snubber circuit may be configured between the first and second power supplies to reduce ringing on the power supplies. In one embodiment, the circuit is a switching regulator and the power supply terminals are internal power supply terminals. The snubber circuit may be programmed to reduce ringing caused by switching currents through parasitic inductances in a package.

Abstract translation: 本公开包括可编程缓冲电路和方法。 在一个实施例中，电路被配置在第一和第二电源端子之间。 可编程缓冲电路可以配置在第一和第二电源之间，以减少电源上的振铃。 在一个实施例中，电路是开关调节器，电源端子是内部电源端子。 缓冲电路可以被编程为减少由开关电流通过封装中的寄生电感引起的振铃。

公开(公告)号：US09455712B2

公开(公告)日：2016-09-27

申请号：US14449393

申请日：2014-08-01

Applicant: QUALCOMM Incorporated

Inventor： Shengyuan Li

IPC: H03L5/00 ,  H03K19/0175 ,  H03K19/00 ,  H03K3/356 ,  H03K19/0185

CPC classification number: H03K19/017545 ,  H03K3/356104 ,  H03K19/0005 ,  H03K19/018528

Abstract: In one embodiment, a circuit comprises a phase interpolator that converts a single-ended input to a pair of symmetric differential signals within a first voltage domain. The circuit further comprises a comparator that converts the symmetric differential signals into single-ended output in a second different voltage domain. In one embodiment, the single ended output of the comparator is configured to be coupled to drive a switching driver in a switching regulator. In one embodiment, the interpolator comprises a first inverter, a second inverter, and a third inverter connected in series. The interpolator further comprises a first resistor and a second resistor connected in series. The second inverter provides a first output signal. Outputs of the first inverter and the third inverter are connected by the series connected resistors. A node between the resistors provides a second output signal. The first and second output signals are inverted and symmetric.

Abstract translation: 在一个实施例中，电路包括相位插值器，其将单端输入转换成第一电压域内的一对对称差分信号。 电路还包括比较器，其将对称差分信号转换成第二不同电压域中的单端输出。 在一个实施例中，比较器的单端输出被配置为耦合以驱动开关稳压器中的开关驱动器。 在一个实施例中，内插器包括串联连接的第一反相器，第二反相器和第三反相器。 内插器还包括串联连接的第一电阻器和第二电阻器。 第二个反相器提供第一个输出信号。 第一个反相器和第三个反相器的输出通过串联电阻连接。 电阻之间的节点提供第二个输出信号。 第一和第二输出信号是反相和对称的。