公开(公告)号：US11081559B1

公开(公告)日：2021-08-03

申请号：US16778546

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Qingqing Liang ,  Sivakumar Kumarasamy ,  George Pete Imthurn ,  Sinan Goktepeli

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.

公开(公告)号：US10600910B2

公开(公告)日：2020-03-24

申请号：US16156729

申请日：2018-10-10

Applicant: QUALCOMM Incorporated

Inventor： Qingqing Liang ,  Ravi Pramod Kumar Vedula ,  Sivakumar Kumarasamy ,  George Pete Imthurn ,  Sinan Goktepeli

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762 ,  H01L29/786 ,  H01L27/12 ,  H01L21/28 ,  H01L29/08

Abstract: An integrated circuit is described. The integrated circuit includes a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET is on a first surface of an insulator layer of the integrated circuit. The MOSFET including a source region, a drain region, and a front gate. The MOSFET also includes an extended drain region between the drain region and a well proximate the front gate. The integrated circuit also includes back gates on a second surface opposite the first surface of the insulator layer. The back gates are overlapped by the extended drain region.

公开(公告)号：US11081582B2

公开(公告)日：2021-08-03

申请号：US16788197

申请日：2020-02-11

Applicant: QUALCOMM Incorporated

Inventor： Qingqing Liang ,  Ravi Pramod Kumar Vedula ,  Sivakumar Kumarasamy ,  George Pete Imthurn ,  Sinan Goktepeli

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.

公开(公告)号：US10903357B2

公开(公告)日：2021-01-26

申请号：US16152105

申请日：2018-10-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  George Pete Imthurn ,  Sivakumar Kumarasamy

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/40 ,  H01L29/786 ,  H04B1/00 ,  H04B1/52 ,  H01L27/12 ,  H04B1/38

Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.