公开(公告)号：US10324131B1

公开(公告)日：2019-06-18

申请号：US15872281

申请日：2018-01-16

Applicant: QUALCOMM Incorporated

Inventor： Lesly Endrinal ,  Rakesh Kinger ,  Joseph Fang ,  Srinivas Patil ,  Lavakumar Ranganathan ,  Chia-Ying Chen

IPC: G01R31/3185 ,  G01R31/3183 ,  G01R31/311 ,  G01R31/3177

Abstract: The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.

公开(公告)号：US11237587B1

公开(公告)日：2022-02-01

申请号：US17121580

申请日：2020-12-14

Applicant: QUALCOMM Incorporated

Inventor： Punit Kishore ,  Ankit Goyal ,  Srinivas Patil

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/14

Abstract: Aspects of the disclosure are directed to clock management. In accordance with one aspect, a clock management apparatus for built-in self-test (BIST) circuitry includes a plurality of local clock controllers; a plurality of clock generators coupled to the plurality of local clock controllers; a master clock controller coupled to the plurality of clock generators; an X-tolerant logical built-in self test (XLBIST) circuit coupled to the master clock controller; and a test access port (TAP) coupled to the XLBIST circuit.