公开(公告)号：US20180067515A1

公开(公告)日：2018-03-08

申请号：US15255329

申请日：2016-09-02

Applicant: QUALCOMM Incorporated

Inventor： Kunal Jain ,  Moitrayee Ghosh ,  Anand Bhat ,  Joseph Fang

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G01R31/31727 ,  G01R31/3187 ,  G01R31/31937 ,  G01R31/44 ,  G06F1/10 ,  G06F1/3237 ,  Y02D10/128

Abstract: Segregated test mode clock gating circuits in a clock distribution network of a circuit for controlling power consumption during testing is provided. To reduce power consumption and current-resistance (IR) drop during testing of a circuit, existing clock gating circuits (e.g., clock gating cells (CGCs)) that control the functional mode of circuit blocks in the circuit are additionally test mode gated for hierarchical testing of the circuit. To avoid the need to gate every CGC in the clock distribution network, only certain segregated clock gating circuits in the clock distribution network may be selected for test mode clock gating according to desired testing hierarchy of the circuit. Test mode clock gating of only certain segregated clock gating circuits in a circuit can reduce the number of test gating circuits providing test mode clock gating to mitigate power consumption and area needed for providing selective testing of circuit blocks in the circuit.

公开(公告)号：US20180074126A1

公开(公告)日：2018-03-15

申请号：US15263059

申请日：2016-09-12

Applicant: QUALCOMM Incorporated

Inventor： Bilal Zafar ,  Rakesh Vattikonda ,  De Lu ,  Venkatasubramanian Narayanan ,  Masoud Zamani ,  Joseph Fang

IPC: G01R31/317 ,  G11C7/22 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318552 ,  G11C7/22

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.

公开(公告)号：US10324131B1

公开(公告)日：2019-06-18

申请号：US15872281

申请日：2018-01-16

Applicant: QUALCOMM Incorporated

Inventor： Lesly Endrinal ,  Rakesh Kinger ,  Joseph Fang ,  Srinivas Patil ,  Lavakumar Ranganathan ,  Chia-Ying Chen

IPC: G01R31/3185 ,  G01R31/3183 ,  G01R31/311 ,  G01R31/3177

Abstract: The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.