公开(公告)号：US10324131B1

公开(公告)日：2019-06-18

申请号：US15872281

申请日：2018-01-16

Applicant: QUALCOMM Incorporated

Inventor： Lesly Endrinal ,  Rakesh Kinger ,  Joseph Fang ,  Srinivas Patil ,  Lavakumar Ranganathan ,  Chia-Ying Chen

IPC: G01R31/3185 ,  G01R31/3183 ,  G01R31/311 ,  G01R31/3177

Abstract: The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.

公开(公告)号：US10605859B2

公开(公告)日：2020-03-31

申请号：US15265744

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Rami Salem ,  Lesly Zaren V. Endrinal ,  Hyeokjin Lim ,  Hadi Bunnalim ,  Robert Kim ,  Lavakumar Ranganathan ,  Mickael Malabry

IPC: G01R31/28 ,  H01L23/50 ,  H01L27/02 ,  H01L27/088 ,  G01R31/311 ,  H01L23/544 ,  H01L23/528 ,  H01L27/118

Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.

公开(公告)号：US09599666B2

公开(公告)日：2017-03-21

申请号：US14525539

申请日：2014-10-28

Applicant: QUALCOMM Incorporated

Inventor： Lavakumar Ranganathan ,  Martin Villafana ,  Lesly Zaren Venturina Endrinal

IPC: G01R31/308 ,  G01R31/311 ,  G01R31/28

CPC classification number: G01R31/311 ,  G01R31/2834 ,  G01R31/2837

Abstract: A method and apparatus for mapping an electronic device. The electronic device is loaded into a test fixture, which may be an automated test equipment (ATE). A laser beam is stepped across locations of interest. At each location of interest a minimum voltage and/or maximum frequency are computed. A contour map of the changes in minimum voltage and maximum frequency across a field of view of the electronic device is generated. Additional embodiments provide signaling a laser scan module during the rising edge of a synchronization pulse to indicate that minimum voltage (Vmin) and maximum frequency (Fmax) specification search data is provided to a laser voltage probe. A Vmin/Fmax module compares the specification search data with the data read from the laser voltage probe and computes a parameter shift value. The laser beam is moved to another location when the falling edge of the synchronization pulse occurs.

公开(公告)号：US10262950B1

公开(公告)日：2019-04-16

申请号：US15913784

申请日：2018-03-06

Applicant: QUALCOMM Incorporated

Inventor： Michael Duane Alston ,  Hadi Bunnalim ,  Lesly Zaren Venturina Endrinal ,  Mickael Sebastien Alain Malabry ,  Lavakumar Ranganathan ,  Rami Fathy Amin Gomaa Salem

IPC: H01L27/118 ,  H01L23/544 ,  H01L29/10 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/28 ,  H01L21/8234

Abstract: A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. The power rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7 nm feature sizes.

公开(公告)号：US20160116531A1

公开(公告)日：2016-04-28

申请号：US14525539

申请日：2014-10-28

Applicant: QUALCOMM Incorporated

Inventor： Lavakumar Ranganathan ,  Martin Villafana ,  Lesly Zaren Venturina Endrinal

IPC: G01R31/311 ,  G01R31/28

CPC classification number: G01R31/311 ,  G01R31/2834 ,  G01R31/2837

Abstract: A method and apparatus for mapping an electronic device. The electronic device is loaded into a test fixture, which may be an automated test equipment (ATE). A laser beam is stepped across locations of interest. At each location of interest a minimum voltage and/or maximum frequency are computed. A contour map of the changes in minimum voltage and maximum frequency across a field of view of the electronic device is generated. Additional embodiments provide signaling a laser scan module during the rising edge of a synchronization pulse to indicate that minimum voltage (Vmin) and maximum frequency (Fmax) specification search data is provided to a laser voltage probe. A Vmin/Fmax module compares the specification search data with the data read from the laser voltage probe and computes a parameter shift value. The laser beam is moved to another location when the falling edge of the synchronization pulse occurs.

Abstract translation: 一种用于映射电子设备的方法和装置。 电子设备被装载到测试夹具中，其可以是自动测试设备（ATE）。 激光束跨越感兴趣的位置。 在感兴趣的每个位置，计算最小电压和/或最大频率。 产生电子设备的视野中的最小电压和最大频率的变化的等高线图。 另外的实施例提供在同步脉冲的上升沿期间向激光扫描模块发信号，以指示将最小电压（Vmin）和最大频率（Fmax）指定搜索数据提供给激光电压探针。 Vmin / Fmax模块将规格搜索数据与从激光电压探头读取的数据进行比较，并计算参数移位值。 当发生同步脉冲的下降沿时，激光束被移动到另一个位置。