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    Face recognition in low light conditions for unlocking an electronic device
    2.
    发明授权
    Face recognition in low light conditions for unlocking an electronic device 有权

    公开(公告)号：US10762336B2

    公开(公告)日：2020-09-01

    申请号：US15967866

    申请日：2018-05-01

    Applicant: QUALCOMM Incorporated

    Inventor： Madhu Yashwanth Boenapalli ,  Venu Madhav Mokkapati ,  Surendra Paravada

    IPC: G06K9/00 ,  H04N5/235 ,  G06T7/136

    Abstract: Certain aspects of the present disclosure provide techniques for performing face recognition in low light conditions using an electronic device. One aspect provides a method including determining if a brightness level within a viewing area of the electronic device satisfies a threshold. The method includes increasing a luminance output of the electronic device from a first luminance level to a second luminance level when the brightness level does not satisfy the threshold. The method includes capturing an image at the second luminance level when the brightness level does not satisfy the threshold. The method includes capturing the image at the first luminance level when the brightness level satisfies the threshold. The method includes detecting a face in the image. The method includes determining if the face corresponds to an authorized user. The method includes unlocking the electronic device when the face corresponds to an authorized user.

    ENHANCED WRITE BUFFER FLUSH SCHEME FOR MEMORY DEVICES WITH HIGH DENSITY STORAGE MEMORY ARCHITECTURE
    4.
    发明申请
    ENHANCED WRITE BUFFER FLUSH SCHEME FOR MEMORY DEVICES WITH HIGH DENSITY STORAGE MEMORY ARCHITECTURE 有权

    公开(公告)号：US20250156334A1

    公开(公告)日：2025-05-15

    申请号：US18509066

    申请日：2023-11-14

    Applicant: QUALCOMM Incorporated

    Inventor： Rajesh Kumar Biswal ,  Manmeet Singh Ahluwalia ,  Surendra Paravada ,  Madhu Yashwanth Boenapalli ,  Sai Praneeth Sreeram

    IPC: G06F12/0891 ,  G06F12/02

    Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

    Universal flash storage read throughput enhancements
    5.
    发明授权
    Universal flash storage read throughput enhancements 有权

    公开(公告)号：US12197771B2

    公开(公告)日：2025-01-14

    申请号：US18298484

    申请日：2023-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Sravani Devineni ,  Sai Praneeth Sreeram ,  Madhu Yashwanth Boenapalli ,  Surendra Paravada

    IPC: G06F12/00 ,  G06F3/06

    Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for updating logical-to-physical (L2P) address mapping tables. Various embodiments may include enabling a device control mode (DCM) of host performance booster (HPB) based on a flush of a writebooster buffer to a normal storage of a UFS device of the UFS system, and updating an L2P address mapping table at a host device of the UFS system while DCM is enabled based on the flush of the writebooster buffer to the normal storage. Some embodiments may include generating a signal having an indicator of a UFS protocol information unit configured to indicate a change in an HPB mode at the UFS device based on the flush of the writebooster buffer to the normal storage, and sending the signal from the UFS device to the host device.

    PACKED COMMANDS FOR COMMUNICATING WITH FLASH MEMORY SYSTEM
    6.
    发明公开
    PACKED COMMANDS FOR COMMUNICATING WITH FLASH MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240302965A1

    公开(公告)日：2024-09-12

    申请号：US18181421

    申请日：2023-03-09

    Applicant: QUALCOMM Incorporated

    Inventor： Madhu Yashwanth Boenapalli ,  Sai Praneeth Sreeram ,  Surendra Paravada

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

    Abstract: This disclosure provides systems, methods, and devices for memory systems that support packed commands for improved performance and reduced power consumption. In a first aspect, a method of accessing data in a flash memory system includes a host memory controller receiving a plurality of commands from a storage driver for execution by a flash memory device; packaging, by the memory controller of the host device, the plurality of commands as a packed command in a packet; and transmitting, by the memory controller of the host device to the flash memory device, the packet comprising the packed command for execution by the flash memory device. The use of packed commands may be based on determining the command acknowledgement delay from the flash memory device exceeds a threshold delay. Other aspects and features are also claimed and described.

    Host performance booster L2P handoff
    7.
    发明授权
    Host performance booster L2P handoff 有权

    公开(公告)号：US11966341B1

    公开(公告)日：2024-04-23

    申请号：US18054249

    申请日：2022-11-10

    Applicant: QUALCOMM Incorporated

    Inventor： Madhu Yashwanth Boenapalli ,  Surendra Paravada ,  Sai Praneeth Sreeram

    IPC: G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F2212/1028 ,  G06F2212/655

    Abstract: Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.

    Effective gear-shifting by queue based implementation
    8.
    发明授权
    Effective gear-shifting by queue based implementation 有权

    公开(公告)号：US10769079B2

    公开(公告)日：2020-09-08

    申请号：US15937814

    申请日：2018-03-27

    Applicant: QUALCOMM Incorporated

    Inventor： Madhu Yashwanth Boenapalli ,  Venu Madhav Mokkapati ,  Surendra Paravada

    IPC: G06F13/16 ,  G06F13/42

    Abstract: In a conventional system with a UFS storage device connected to a UFS host over one or more lanes, the lanes can support different transmission speeds, referred to as gears. The UFS host shifts lanes and gears based on the type of request it receives. When the requests arrive in random order of gear requirements, the frequent shifting of the lanes and gears causes significant power consumption. To address this issue, it is proposed to implement a queue-based shifting in which arriving requests may be queued based on their gear requirements. When a queue is selected, multiple requests in the selected queue, which are all of same or similar gear requirement, can be served. This can reduce the frequency of gear shifting, and hence reduce power consumption.

    SYSTEMS AND METHODS FOR FAST MEMORY ACCESS
    9.
    发明申请
    SYSTEMS AND METHODS FOR FAST MEMORY ACCESS 有权

    公开(公告)号：US20230134404A1

    公开(公告)日：2023-05-04

    申请号：US17453572

    申请日：2021-11-04

    Applicant: QUALCOMM Incorporated

    Inventor： Madhu Yashwanth Boenapalli ,  Sai Praneeth Sreeram ,  Surendra Paravada

    IPC: G06F12/084 ,  G06F12/02 ,  G06F15/78 ,  G06F13/16

    Abstract: Systems and methods for fast memory access are disclosed. In one aspect, a processor such as, for example, a control circuit in a system on a chip (SoC) that couples to an external memory such as, for example a Universal File System (UFS) memory (e.g., a NAND flash memory) with a partial logical to physical (L2P) mapping table stored in the external memory as well as a local L2P mapping table stored in a local memory (e.g., dynamic random-access memory (DRAM)). The control circuit may evaluate what percentage of entries in the local L2P mapping table are active compared to inactive. If the number of inactive exceeds the number of active, the control circuit may send a read command without accessing the local L2P mapping table.

    EMERGENCY OR STEALTH RESPONSES TRIGGERED BY FINGERPRINT SENSOR
    10.
    发明申请
    EMERGENCY OR STEALTH RESPONSES TRIGGERED BY FINGERPRINT SENSOR 有权

    公开(公告)号：US20230085885A1

    公开(公告)日：2023-03-23

    申请号：US17448195

    申请日：2021-09-20

    Applicant: QUALCOMM Incorporated

    Inventor： Sai Praneeth Sreeram ,  Surendra Paravada ,  Madhu Yashwanth Boenapalli ,  Bipul Tarafdar

    IPC: H04W4/90 ,  G06F3/048 ,  G06K9/00

    Abstract: A method may involve receiving fingerprint sensor data from a fingerprint sensor system, detecting, according to the fingerprint sensor data, a presence of a digit on an outer surface of the apparatus in a fingerprint sensor system area; determining, according to the fingerprint sensor data, a digit force or a digit pressure of the digit on the outer surface of the apparatus; and making, according to the fingerprint sensor data, a time threshold determination. The time threshold determination may involve determining whether a length of time during which the digit force exceeds a threshold digit force or during which the digit pressure exceeds a threshold digit pressure is greater than or equal to a threshold length of time. The method may involve determining, based at least in part on the time threshold determination, whether to enable one or more emergency response functions of the apparatus.

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