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    Method and mechanism for implementing electronic designs having power information specifications background
    1.
    发明授权
    Method and mechanism for implementing electronic designs having power information specifications background 有权
    实现具有电力信息规格背景的电子设计的方法和机制

    公开(公告)号：US08516422B1

    公开(公告)日：2013-08-20

    申请号：US12815239

    申请日：2010-06-14

    申请人： Qi Wang ,  Ankur Gupta ,  Pinhong Chen ,  Christina Chu ,  Manish Pandey ,  Huan-Chih Tsai ,  Sandeep Bhatia ,  Yonghao Chen ,  Steven Sharp ,  Vivek Chickermane ,  Patrick Gallagher

    发明人： Qi Wang ,  Ankur Gupta ,  Pinhong Chen ,  Christina Chu ,  Manish Pandey ,  Huan-Chih Tsai ,  Sandeep Bhatia ,  Yonghao Chen ,  Steven Sharp ,  Vivek Chickermane ,  Patrick Gallagher

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5081 ,  G06F2217/78

    摘要： A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

    摘要翻译： 一种用于实现用于IC的功率相关信息的单个文件格式的方法，包括：在非暂时性计算机可读存储设备中的至少一个设计文件中提供电路设计; 在与所述至少一个设计文件分离的并且指定所述电路设计中的多个电力域的所述计算机可读存储设备中的文件中提供电力相关设计信息，每个电力域包括来自所述电路内的一个或多个设计对象实例 并且指定多个功率模式，每个功率模式对应于多个指定功率域的开/关状态的不同组合，并且指定相对于相应功率域的隔离行为; 并且使用计算机将功率控制电路添加到实现功率规范信息中指定的功率域和功率模式以及隔离行为的电路设计。

    High level IC design with power specification and power source hierarchy
    5.
    发明授权
    High level IC design with power specification and power source hierarchy 有权
    具有电源规格和电源层级的高级IC设计

    公开(公告)号：US07954078B1

    公开(公告)日：2011-05-31

    申请号：US11771953

    申请日：2007-06-29

    申请人： Qi Wang ,  Pinhong Chen ,  Mitchell W. Hines

    发明人： Qi Wang ,  Pinhong Chen ,  Mitchell W. Hines

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/78

    摘要： A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.

    摘要翻译： 一种在计算机可读存储器中产生信息结构的方法，其指定包括在计算机可读存储器中编码的多个功能实例的RTL电路设计的电源层级信息，包括：在所述存储器内提供所述RTL设计的各个功能实例与相应的 功率域，以便相对于RTL设计定义相应的主要功率域; 在存储器中指定相应的次级电源域; 以及在存储器内提供表示各个主电力域和对应的相应次级电力域之间的各个电源关系的关联。

    SMALL MOLECULE COMPOUNDS AS BROAD-SPECTRUM INHIBITORS OF METALLO-BETA-LACTAMASES
    6.
    发明申请
    SMALL MOLECULE COMPOUNDS AS BROAD-SPECTRUM INHIBITORS OF METALLO-BETA-LACTAMASES 审中-公开
    小分子化合物作为METALLO-BETA-LACTAMASES的广谱光谱抑制剂

    公开(公告)号：US20120329842A1

    公开(公告)日：2012-12-27

    申请号：US13332793

    申请日：2011-12-21

    申请人： Yongcheng Song ,  Timothy Palzkill ,  Pinhong Chen ,  Lori Horton

    发明人： Yongcheng Song ,  Timothy Palzkill ,  Pinhong Chen ,  Lori Horton

    IPC分类号： A61K31/426 ,  C07D277/56 ,  A61P31/04 ,  C12N9/99

    CPC分类号： A61K31/425

    摘要： The present invention concerns methods and/or compositions for treatment and/or prevention of bacterial infection wherein the bacteria has at least one metallo-β-lactamase. The bacteria are provided with an inhibitor of the metallo-β-lactamase, for example in conjunction with an antibiotic that targets the bacteria. The bacteria may be a drug-resistant strain or susceptible to becoming a drug-resistant strain. In specific embodiments, the bacteria is Pseudomonas or Acinetobacter spp.

    摘要翻译： 本发明涉及用于治疗和/或预防细菌感染的方法和/或组合物，其中细菌具有至少一种金属 - β-内酰胺酶。 细菌具有金属 - β-内酰胺酶的抑制剂，例如与针对细菌的抗生素结合。 细菌可能是耐药菌株或易成为耐药菌株。 在具体实施方案中，细菌是假单胞菌属或不动杆菌属。

    Method for estimating peak crosstalk noise based on separate crosstalk model
    7.
    发明授权
    Method for estimating peak crosstalk noise based on separate crosstalk model 失效
    基于单独串扰模型估计峰值串扰噪声的方法

    公开(公告)号：US06971076B2

    公开(公告)日：2005-11-29

    申请号：US10313866

    申请日：2002-12-05

    申请人： Pinhong Chen

    发明人： Pinhong Chen

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Crosstalk noise peaks in output signals of nets of an integrated circuit layout design are estimated by first processing the design to estimate resistances and capacitances of the nets. The design is then processed to identify each aggressor net having at least one section that is proximate to a section of a victim net. A separate aggressor model is then generated for each proximate aggressor net section, the aggressor model including a current source and a capacitor. The design is then processed to identify each victim net that is proximate any aggressor net and a separate crosstalk model is generated for each identified victim net. The crosstalk model for each victim net includes the victim net's estimated resistances and capacitances and incorporates the aggressor model of each aggressor net section that is proximate to a section of the identified victim net. The crosstalk model for each identified victim net is then evaluated to determine a response to a signal applied as input to the victim net of a victim net output signal. The peak crosstalk noise in each identified victim net is estimated based on the response of the net's output signal.

    摘要翻译： 通过首先处理设计来估计网络的电阻和电容来估计集成电路布局设计的网络的输出信号中的串扰噪声峰值。 然后处理该设计以识别具有至少一个接近受害网的一部分的部分的每个侵略者网。 然后针对每个邻近的侵略者网段产生单独的攻击者模型，攻击者模型包括电流源和电容器。 然后处理该设计以识别与任何侵略者网络相邻的每个受害者网络，并且为每个识别的受害者网络生成单独的串扰模型。 每个受害者网络的串扰模型包括受害者网络的估计电阻和电容，并且包含接近识别的受害者网络的一部分的每个侵略者网段的侵略者模型。 然后评估每个确定的受害者网络的串扰模型，以确定对作为受害者净输出信号的受害者网络的输入的信号的响应。 基于网络输出信号的响应，估计每个确定的受害者网络中的峰值串扰噪声。

    Method and apparatus for power consumption optimization for integrated circuits
    8.
    发明授权
    Method and apparatus for power consumption optimization for integrated circuits 有权
    集成电路功耗优化方法及装置

    公开(公告)号：US07551985B1

    公开(公告)日：2009-06-23

    申请号：US11590068

    申请日：2006-10-30

    申请人： Pinhong Chen ,  Wilsin Gosti

    发明人： Pinhong Chen ,  Wilsin Gosti

    IPC分类号： G06F19/00

    CPC分类号： G06F17/505 ,  G06F2217/78

    摘要： Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by modeling both internal and external signal paths in an integrated circuit which has a number of power domains. The relationship between slack and voltage for the external and internal signal propagation paths is modeled, typically as a linear approximation. The integrated circuit design is then abstracted to a simplified form in terms of power domain relations and a model is created and solved iteratively using, e.g., linear programming, of different voltage levels for each power domain and including the slack values and their relationship between the changes in voltage and slack, for both the internal and external paths.

    摘要翻译： 用于找到对集成电路的所有功率域的电压分配的方法和装置，使得集成电路设计的功耗最小化并且满足时序要求（信号传播延迟或松弛）。 这通过对具有多个功率域的集成电路中的内部和外部信号路径进行建模来完成。 外部和内部信号传播路径的松弛和电压之间的关系被建模，通常是线性近似。 在功率域关系方面，集成电路设计被抽象为简化形式，并且使用例如线性编程，针对每个功率域的不同电压电平迭代地创建和解决模型，并且包括松弛值以及它们之间的关系 内部和外部路径的电压和松弛变化。

    Method of estimating path delays in an IC
    9.
    发明授权
    Method of estimating path delays in an IC 失效
    估计IC中路径延迟的方法

    公开(公告)号：US07082587B2

    公开(公告)日：2006-07-25

    申请号：US10323399

    申请日：2002-12-18

    申请人： Pinhong Chen ,  Chin-Chi Teng

    发明人： Pinhong Chen ,  Chin-Chi Teng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5022

    摘要： To estimate path delays within an IC, a serial database is first created to hold and read out RC extraction data for nets within the IC in an order in which the RC extraction data will be needed when estimating path delays. Thereafter, as the RC extraction data is sequentially read out of the database for each net, the path delay though each section of the net is computed and added to the estimated path delay for each signal path including that net section. The RC extraction data for each net is accessed and accessed only once, thereby minimizing the processing time needed to perform timing analysis by minimizing hard disk read accesses when the RC extraction database resides on a hard disk.

    摘要翻译： 为了估计IC内的路径延迟，首先创建串行数据库，以便在估计路径延迟时按照RC提取数据的顺序保存和读出IC内的网络的RC提取数据。 此后，随着每个网络从数据库中顺序地读取RC提取数据，计算网络的每个部分的路径延迟并将其加到包括该网段的每个信号路径的估计路径延迟中。 每个网络的RC提取数据被访问和访问一次，从而通过在RC提取数据库驻留在硬盘上时最小化硬盘读取访问来最小化执行时序分析所需的处理时间。