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    SARS-CoV-2 TEST KIT FOR RT-qPCR ASSAYS
    1.
    发明申请
    SARS-CoV-2 TEST KIT FOR RT-qPCR ASSAYS 有权

    公开(公告)号：US20210332444A1

    公开(公告)日：2021-10-28

    申请号：US17233423

    申请日：2021-04-16

    申请人： Qing Sun ,  Michael Y. Sha ,  Hui Ren ,  Jonathan Li ,  Aiguo Zhang

    发明人： Qing Sun ,  Michael Y. Sha ,  Hui Ren ,  Jonathan Li ,  Aiguo Zhang

    IPC分类号： C12Q1/70

    摘要： The present invention provides synthetic nucleic acid sequences comprising 10-30 nucleotides of the N1 and N2 gene regions and/or the 3′ non-coding region of the SARS-associated coronavirus Cov-2 (SARS-CoV-2) genome, and a synthetic nucleic acid sequence comprising 10-30 nucleotides of a nucleic acid sequence that is complementary to at least one of those regions. Also provided are compositions comprising the sequences, and uses of the sequences in diagnostic kits. The present invention further provides a primer and probe set for determining the presence or absence of SARS-associated coronavirus Cov-2 in a biological sample, wherein the primer set comprises at least one of the synthetic nucleic acid sequences. Also provided are a composition comprising the primer and probe set, and use of the primer and probe set in a diagnostic kit. Finally, the present invention provides kits and methods for determining the presence or absence of SARS-associated coronavirus Cov-2 (SARS-CoV-2) in a biological sample.

    Method and device for data transmission between register files
    6.
    发明授权
    Method and device for data transmission between register files 有权
    寄存器文件之间数据传输的方法和设备

    公开(公告)号：US09501278B2

    公开(公告)日：2016-11-22

    申请号：US14008159

    申请日：2011-08-22

    申请人： Lihuang Li ,  Hui Ren ,  Chunyu Tian

    发明人： Lihuang Li ,  Hui Ren ,  Chunyu Tian

    IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30079 ,  G06F9/30032 ,  G06F9/3013 ,  G06F9/3867

    摘要： The present disclosure discloses a method and device for data transmission between register files. The method includes that: data in a source register file are read at a Stage i of a pipeline; and the read data are transmitted to a destination register file using an idle instruction pipeline. With the method of the present disclosure, data and mask information are transmitted using an idle instruction pipeline, without addition of extra registers for data and control information buffering, thus reducing logic consumption as well as increasing utilization of an existing functional unit.

    摘要翻译： 本公开公开了一种用于在寄存器文件之间进行数据传输的方法和装置。 该方法包括：在管道的第i阶段读取源寄存器文件中的数据; 并且使用空闲指令流水线将读取的数据发送到目的地寄存器文件。 利用本公开的方法，使用空闲指令流水线传输数据和掩码信息，而不添加用于数据和控制信息缓冲的附加寄存器，从而减少逻辑消耗以及增加现有功能单元的利用。

    Device and method for implementing address buffer management of processor
    7.
    发明授权
    Device and method for implementing address buffer management of processor 有权
    用于实现处理器地址缓冲区管理的设备和方法

    公开(公告)号：US09389859B2

    公开(公告)日：2016-07-12

    申请号：US14005719

    申请日：2011-08-24

    申请人： Lea Hwang Lee ,  Chunyu Tian ,  Hui Ren

    发明人： Lea Hwang Lee ,  Chunyu Tian ,  Hui Ren

    IPC分类号： G06F9/30 ,  G06F9/345

    CPC分类号： G06F9/30043 ,  G06F9/30 ,  G06F9/3455

    摘要： The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the disclosure, the hardware costs of the processor are reduced and design requirements of the processor's time sequence and energy efficiency are met.

    摘要翻译： 本发明提供了一种用于实现处理器的地址缓冲器管理的设备，包括：汇编器，被配置为当汇编器对地址自动增量值和边界值的设置指令进行编码时，执行操作以获得中间值，并且封装中间值 进入地址自动递增值和边界值的设置指令; 以及处理器，被配置为根据中间值确定是否执行地址自动递增操作或地址自动递减操作，以便实现地址缓冲器管理。 本公开还提供了一种用于实现处理器的地址缓冲器管理的方法，包括：处理器对地址自动增量值和边界值的设置指令进行解码以获得中间值，并根据中间值确定是否执行 地址自动递增运算或地址自动递减运算，以便实现地址缓存管理。 通过本发明的装置和方法，降低了处理器的硬件成本，满足了处理器的时序和能量效率的设计要求。

    Method and Device for Data Transmission Between Register Files
    8.
    发明申请
    Method and Device for Data Transmission Between Register Files 有权
    寄存器文件之间数据传输的方法和装置

    公开(公告)号：US20140019730A1

    公开(公告)日：2014-01-16

    申请号：US14008159

    申请日：2011-08-22

    申请人： Lihuang Li ,  Hui Ren ,  Chunyu Tian

    发明人： Lihuang Li ,  Hui Ren ,  Chunyu Tian

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30079 ,  G06F9/30032 ,  G06F9/3013 ,  G06F9/3867

    摘要： The present disclosure discloses a method and device for data transmission between register files. The method includes that: data in a source register file are read at a Stage i of a pipeline; and the read data are transmitted to a destination register file using an idle instruction pipeline. With the method of the present disclosure, data and mask information are transmitted using an idle instruction pipeline, without addition of extra registers for data and control information buffering, thus reducing logic consumption as well as increasing utilization of an existing functional unit.

    摘要翻译： 本公开公开了一种用于在寄存器文件之间进行数据传输的方法和装置。 该方法包括：在管道的第i阶段读取源寄存器文件中的数据; 并且使用空闲指令流水线将读取的数据发送到目的地寄存器文件。 利用本公开的方法，使用空闲指令流水线传输数据和掩码信息，而不添加用于数据和控制信息缓冲的附加寄存器，从而减少逻辑消耗以及增加现有功能单元的利用。

    DEVICE AND METHOD FOR IMPLEMENTING ADDRESS BUFFER MANAGEMENT OF PROCESSOR
    9.
    发明申请
    DEVICE AND METHOD FOR IMPLEMENTING ADDRESS BUFFER MANAGEMENT OF PROCESSOR 有权
    执行处理器地址缓冲区管理的设备和方法

    公开(公告)号：US20140013084A1

    公开(公告)日：2014-01-09

    申请号：US14005719

    申请日：2011-08-24

    申请人： Lihuang Li ,  Chunyu Tian ,  Hui Ren

    发明人： Lihuang Li ,  Chunyu Tian ,  Hui Ren

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30043 ,  G06F9/30 ,  G06F9/3455

    摘要： The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the disclosure, the hardware costs of the processor are reduced and design requirements of the processor's time sequence and energy efficiency are met.

    摘要翻译： 本发明提供了一种用于实现处理器的地址缓冲器管理的设备，包括：汇编器，被配置为当汇编器对地址自动增量值和边界值的设置指令进行编码时，执行操作以获得中间值，并且封装中间值 进入地址自动递增值和边界值的设置指令; 以及处理器，被配置为根据中间值确定是否执行地址自动递增操作或地址自动递减操作，以便实现地址缓冲器管理。 本公开还提供了一种用于实现处理器的地址缓冲器管理的方法，包括：处理器对地址自动增量值和边界值的设置指令进行解码以获得中间值，并根据中间值确定是否执行 地址自动递增运算或地址自动递减运算，以便实现地址缓存管理。 通过本发明的装置和方法，降低了处理器的硬件成本，满足了处理器的时序和能量效率的设计要求。