公开(公告)号：US06951812B2

公开(公告)日：2005-10-04

申请号：US10739980

申请日：2003-12-17

申请人： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

发明人： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

摘要翻译： 在半导体主体的水平表面中的集成电路的结构和制造方法，包括在所述半导体主体上方的电介质层，以及穿过电介质层的大致垂直的孔，该孔具有侧壁和底部。 阻挡层位于电介质层的上方，该电介质层包括孔内孔和孔底部的侧壁; 阻挡层可操作以密封铜。 铜掺杂过渡层位于阻挡层上方; 过渡层具有高于纯铜的电阻率，并且可操作以牢固地结合到铜和阻挡层，从而改善电迁移可靠性。 所述孔的其余部分填充有铜。 孔可以是沟槽或沟槽和通孔。

公开(公告)号：US06693356B2

公开(公告)日：2004-02-17

申请号：US10107630

申请日：2002-03-27

申请人： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

发明人： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

IPC分类号： H01L2352

CPC分类号： H01L21/76831 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

摘要翻译： 在半导体主体的水平表面中的集成电路的结构和制造方法，包括在所述半导体主体上方的电介质层，以及穿过电介质层的大致垂直的孔，该孔具有侧壁和底部。 阻挡层位于电介质层的上方，该电介质层包括孔内孔和孔底部的侧壁; 阻挡层可操作以密封铜。 铜掺杂过渡层位于阻挡层上方; 过渡层具有高于纯铜的电阻率，并且可操作以牢固地结合到铜和阻挡层，从而改善电迁移可靠性。 所述孔的其余部分填充有铜。 孔可以是沟槽或沟槽和通孔。

公开(公告)号：US06548400B2

公开(公告)日：2003-04-15

申请号：US09917364

申请日：2001-07-27

申请人： Kenneth D. Brennan ,  Qing-Tang Jiang

发明人： Kenneth D. Brennan ,  Qing-Tang Jiang

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one photomask for creating vias and trenches is needed instead of the conventional two masks. The function of the second mask is replaced by a series of plasma etch steps, which exploit differential etch rates for areas which are open relative to areas which are narrow and constricted. As a technical advantage of the invention, each interconnection created by the method of the invention is a structure of wider trenches and narrower vias, wherein the diameter of the vias is approximately the same as the narrowest width of the reverse trench pattern, and each via is centered within the trench. The reverse trench pattern surrounding the via is approximately twice the width of the via diameter.

摘要翻译： 一种用于在集成电路中制造电路互连的方法，其包括金属线之间的垂直通孔和水平沟槽，其中仅需要一个用于产生通路和沟槽的光掩模，而不是传统的两个掩模。 第二掩模的功能被一系列等离子体蚀刻步骤代替，这些步骤利用相对于狭窄和收缩的区域开放的区域的差别蚀刻速率。作为本发明的技术优点，每个互连通过 本发明是更宽的沟槽和较窄通孔的结构，其中通孔的直径与反向沟槽图案的最窄宽度大致相同，并且每个通孔在沟槽内居中。 围绕通孔的反向沟槽图案大约是通孔直径宽度的两倍。

公开(公告)号：US07118925B2

公开(公告)日：2006-10-10

申请号：US11008900

申请日：2004-12-10

申请人： Kenneth D. Brennan ,  Satyavolu S. Papa Rao

发明人： Kenneth D. Brennan ,  Satyavolu S. Papa Rao

IPC分类号： H01L21/00

CPC分类号： H01L23/5227 ,  H01F17/0033 ,  H01F41/046 ,  H01L23/5223 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250′, forming a ferromagnetic capacitor top plate 20a and a ferromagnetic core 20b, forming a top portion of the induction coil 50b plus vias 50c that couple the top portion of the induction coil 50b to the bottom portion of the induction coil 50c.

摘要翻译： 一种在半导体晶片上制造集成电路的方法。 该方法包括形成电容器50a的底板和感应线圈50a的底部，形成蚀刻停止层250'，形成铁磁电容器顶板20A和铁磁芯20b，形成顶部 感应线圈50b加上将感应线圈50b的顶部连接到感应线圈50c的底部的通孔50c。

公开(公告)号：US06465339B2

公开(公告)日：2002-10-15

申请号：US09216240

申请日：1998-12-18

申请人： Keith Brankner ,  Kenneth D. Brennan ,  Yvette Shaw

发明人： Keith Brankner ,  Kenneth D. Brennan ,  Yvette Shaw

IPC分类号： H01L2144

CPC分类号： H01L23/5222 ,  H01L21/31604 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique is described for providing cavities between the conducting paths of an integrated semiconductor circuit. These cavities can have air or a gas trapped therein to decrease the dielectric constant between two conducting paths. After forming the conducting paths, an etchable fill material formed between and over the conducting paths. An oxide cap is formed over the fill material. Conducting plugs, extending through the fill material and the oxide cap, and electrically coupled to the conducting paths are formed. A photo-resist layer applied over the conducting plugs and the oxide cap. The photo-resist layer is structured to permit access to the oxide cap between the conducting plugs. A “pin-hole” is fabricated through the oxide cap and the fill material exposed by the “pin-hole” is etched away. The “pin-hole” is plugged with additional oxide cap material and a surface is then formed on the oxide cap exposing the conducting plugs. This structure is then ready for additional processing.

摘要翻译： 描述了一种用于在集成半导体电路的导电路径之间提供空腔的技术。 这些空腔可以具有空气或被捕获在其中的气体以降低两个传导路径之间的介电常数。 在形成导电路径之后，形成在导电路径之间和之上的可蚀刻填充材料。 在填充材料上形成氧化物盖。 形成延伸穿过填充材料和氧化物盖并且电耦合到导电路径的导电插头。 施加在导电插塞和氧化物盖上的光致抗蚀剂层。 光致抗蚀剂层被构造成允许接触导电插塞之间的氧化物盖。 通过氧化物盖制造“针孔”，并且通过“针孔”暴露的填充材料被蚀刻掉。 “针孔”用附加的氧化物盖材料堵塞，然后在暴露导电插塞的氧化物盖上形成表面。 然后，该结构可以进行额外的处理。

公开(公告)号：US07969274B2

公开(公告)日：2011-06-28

申请号：US12202665

申请日：2008-09-02

申请人： Kenneth D. Brennan ,  Satyavolu S. Papa Rao ,  Byron Williams

发明人： Kenneth D. Brennan ,  Satyavolu S. Papa Rao ,  Byron Williams

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/008 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49073 ,  H01L2924/00

摘要： An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed over or within the first isolation layer (106, 114). The first core plate (104) includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer (108) overlies the first isolation layer and an inductor coil (102) composed of a conductive material layer (118) is formed within the second isolation layer (108). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil (102).

摘要翻译： 公开了一种形成在集成电路（100）中的电感器结构（102），并且包括设置在第一隔离层（106,114）上或第一隔离层（106,114）内的第一隔离层（106）和第一芯板（104）。 第一芯板（104）包括由导电铁磁材料层构成的多个电耦合导电迹线。 第二隔离层（108）覆盖第一隔离层，并且在第二隔离层（108）内形成由导电材料层（118）构成的电感线圈（102）。 可以在线圈上形成另一个芯板。 一个或多个芯板增加电感线圈（102）的电感（L）。

公开(公告)号：US5998297A

公开(公告)日：1999-12-07

申请号：US947489

申请日：1997-10-10

申请人： Kenneth D. Brennan

发明人： Kenneth D. Brennan

IPC分类号： C23F4/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/44

CPC分类号： H01L21/02071 ,  C23F4/00 ,  H01L21/32136

摘要： An embodiment of the instant invention is a method of etching a conductive structure comprised of copper and overlying a semiconductor substrate, the method comprising the step of: subjecting the conductive structure to a combination of plasma, an etchant, and a gaseous aluminum source. Preferably, the conductive structure is comprised of aluminum and copper (more preferably, it is comprised of aluminum and 1 to 4% by weight copper) or it may be substantially comprised of substantially pure copper. In addition, the etchant is preferably introduced into the process chamber in a gaseous state and is comprised of Cl.sub.2. The gaseous aluminum source may be comprised of: DMAH, trimethylaluminum, dimethylalane, trimethylaminealine, dimethylethylaminealane, dimethylethylaminedimethylalane, or AlCl.sub.3.

摘要翻译： 本发明的一个实施方案是蚀刻由铜构成并覆盖半导体衬底的导电结构的方法，该方法包括以下步骤：对导电结构进行等离子体，蚀刻剂和气态铝源的组合。 优选地，导电结构由铝和铜组成（更优选地，其由铝和1至4重量％的铜组成），或者其可以基本上由基本上纯的铜组成。 此外，蚀刻剂优选以气态引入处理室，并且由Cl 2组成。 气态铝源可以由以下物质组成：DMAH，三甲基铝，二甲基亚砜，三甲基胺，二甲基乙基胺，二甲基乙基己基二甲基铝或AlCl 3。

公开(公告)号：US07397107B2

公开(公告)日：2008-07-08

申请号：US11340278

申请日：2006-01-26

申请人： Kenneth D. Brennan ,  Satyavolu S. Papa Rao

发明人： Kenneth D. Brennan ,  Satyavolu S. Papa Rao

IPC分类号： H01L29/00

CPC分类号： H01L23/5227 ,  H01F17/0033 ,  H01F41/046 ,  H01L23/5223 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250′, and a ferromagnetic top plate 20a.

摘要翻译： 具有底板50a，介电层250'和铁磁顶板20a的集成电路电容器。

公开(公告)号：US06911389B2

公开(公告)日：2005-06-28

申请号：US10246061

申请日：2002-09-18

申请人： Kenneth D. Brennan ,  Paul Gillespie

发明人： Kenneth D. Brennan ,  Paul Gillespie

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/7681 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming vias, trenches, and interconnects through diffusion barrier, etch-stop, and dielectric materials for interconnection of electrical devices in dual damascene structures of a semiconductor device. A buried via mask at the etch-stop level provides openings with two or more adjacent via misalignment error regions merged into rectangular windows aligned orthogonal to a long axis of the underlying conductive features of a first metal level. The rectangular windows used together with openings in a hard mask form via portions, and the openings in the hard mask provide trench portions. Via and trench portions coincide during trench or via etch, as well as during hard mask or etch-stop layer etch together forming an interconnect cavity, which may then be filled with a conductive material to provide a conductive interconnect between the conductive feature of the first metal level and a second metal level.

摘要翻译： 公开了用于通过扩散屏障，蚀刻停止和介电材料形成通孔，沟槽和互连的方法，用于半导体器件的双镶嵌结构中的电器件的互连。 在蚀刻停止水平处的掩埋通孔掩模提供具有两个或更多个相邻的通孔未对准误差区域的开口，该相邻的通孔未对准误差区域被合并成与第一金属水平的底部导电特征的长轴正交排列的矩形窗口。 与通过部分的硬掩模形式的开口一起使用的矩形窗口，并且硬掩模中的开口提供沟槽部分。 通孔和沟槽部分在沟槽或通孔蚀刻期间重合，以及在硬掩模或蚀刻停止层蚀刻期间一起形成互连腔，然后可以用导电材料填充以在第一和第二导电特征之间提供导电互连 金属水平和第二金属水平。

公开(公告)号：US06903918B1

公开(公告)日：2005-06-07

申请号：US10828139

申请日：2004-04-20

申请人： Kenneth D. Brennan

发明人： Kenneth D. Brennan

IPC分类号： H01G4/228

CPC分类号： H01G4/228 ,  H01L23/5223 ,  H01L23/5225 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A shielded planar capacitor structure (202) is discussed, formed within a Faraday cage (210) in an integrated circuit device (200). The capacitor structure (202) reduces parasitic capacitances within the integrated circuit device (200). The capacitor (202) comprises a capacitor stack (102) formed between a first and second metal layers (230,232) of the integrated circuit. The capacitor stack (102) has a first conductive layer formed from a third metal layer (106) disposed between the first and second metal layers (230,232) of the integrated circuit, a dielectric isolation layer (110) disposed upon the first conductive layer (106); and a second conductive layer (112) disposed upon the dielectric isolation layer (110) and overlying the first conductive layer (106). The structure (202) further has a first and second isolation layers (104,114) disposed upon opposite sides of the capacitor stack (102). The Faraday cage (210) is formed between the first and second metal layers (230,232) of the integrated circuit (200), comprising a first and second shield layers (402,414) each having a plurality of mutually electrically conductive spaced apart traces (404). The first and second isolation layers (404,414) and the capacitor stack (102,434) are sandwiched between the first and second shield layers (402,414). Conductive elements (432) are distributed around the periphery of the capacitor stack (102,434) and the first and second isolation layers (404,412). The conductive traces (424) of the first shield layer (402) are connected to the conductive traces (424) of the second shield layer (414) through the conductive elements (432).

摘要翻译： 讨论了屏蔽平面电容器结构（202），其形成在集成电路器件（200）中的法拉第笼（210）内。 电容器结构（202）降低集成电路器件（200）内的寄生电容。 电容器（202）包括形成在集成电路的第一和第二金属层（230,232）之间的电容器堆叠（102）。 电容器堆叠（102）具有由设置在集成电路的第一和第二金属层（230,232）之间的第三金属层（106）形成的第一导电层，设置在第一导电层上的介电隔离层（110） 106）; 以及设置在所述介电隔离层（110）上并且覆盖所述第一导电层（106）的第二导电层（112）。 结构（202）还具有设置在电容器堆叠（102）的相对侧上的第一和第二隔离层（104,114）。 法拉第笼（210）形成在集成电路（200）的第一和第二金属层（230,232）之间，包括第一和第二屏蔽层（402,414），每个屏蔽层具有多个相互导电的间隔开的迹线（404） 。 第一和第二隔离层（404,414）和电容器堆叠（102,434）夹在第一和第二屏蔽层（402,414）之间。 导电元件（432）围绕电容器堆叠（102,434）和第一和第二隔离层（404,412）的周边分布。 第一屏蔽层（402）的导电迹线（424）通过导电元件（432）连接到第二屏蔽层（414）的导电迹线（424）。