公开(公告)号：US06951812B2

公开(公告)日：2005-10-04

申请号：US10739980

申请日：2003-12-17

申请人： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

发明人： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

摘要翻译： 在半导体主体的水平表面中的集成电路的结构和制造方法，包括在所述半导体主体上方的电介质层，以及穿过电介质层的大致垂直的孔，该孔具有侧壁和底部。 阻挡层位于电介质层的上方，该电介质层包括孔内孔和孔底部的侧壁; 阻挡层可操作以密封铜。 铜掺杂过渡层位于阻挡层上方; 过渡层具有高于纯铜的电阻率，并且可操作以牢固地结合到铜和阻挡层，从而改善电迁移可靠性。 所述孔的其余部分填充有铜。 孔可以是沟槽或沟槽和通孔。

公开(公告)号：US06693356B2

公开(公告)日：2004-02-17

申请号：US10107630

申请日：2002-03-27

申请人： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

发明人： Qing-Tang Jiang ,  Robert Tsu ,  Kenneth D. Brennan

IPC分类号： H01L2352

CPC分类号： H01L21/76831 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

摘要翻译： 在半导体主体的水平表面中的集成电路的结构和制造方法，包括在所述半导体主体上方的电介质层，以及穿过电介质层的大致垂直的孔，该孔具有侧壁和底部。 阻挡层位于电介质层的上方，该电介质层包括孔内孔和孔底部的侧壁; 阻挡层可操作以密封铜。 铜掺杂过渡层位于阻挡层上方; 过渡层具有高于纯铜的电阻率，并且可操作以牢固地结合到铜和阻挡层，从而改善电迁移可靠性。 所述孔的其余部分填充有铜。 孔可以是沟槽或沟槽和通孔。

公开(公告)号：US06653676B2

公开(公告)日：2003-11-25

申请号：US09918228

申请日：2001-07-30

申请人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

发明人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

IPC分类号： H01L27108

CPC分类号： H01L28/75 ,  H01L21/28518 ,  H01L21/76897 ,  H01L28/55 ,  H01L28/90

摘要： The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.

公开(公告)号：US06168985A

公开(公告)日：2001-01-02

申请号：US09332894

申请日：1999-06-15

申请人： Isamu Asano ,  Robert Tsu

发明人： Isamu Asano ,  Robert Tsu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。

公开(公告)号：US6096597A

公开(公告)日：2000-08-01

申请号：US14204

申请日：1998-01-28

申请人： Robert Tsu ,  William R. McKee ,  Shimpei Iijima ,  Isamu Asano ,  Masato Kunitomo ,  Tsuyoshi Tamaru

发明人： Robert Tsu ,  William R. McKee ,  Shimpei Iijima ,  Isamu Asano ,  Masato Kunitomo ,  Tsuyoshi Tamaru

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L27/108

CPC分类号： H01L28/40 ,  H01L28/55 ,  H01L28/82

摘要： In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O.sub.2 plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be useful in forming a capacitor 12 dielectric 24. In turn, the capacitor could be used in a DRAM memory device.

摘要翻译： 在一个实施例中，本发明提供了一种处理电介质层24的方法。首先，在进行O 2等离子体的同时加热电介质层。 之后，在受到臭氧环境的影响的同时加热电介质层。 该方法可用于形成电容器12电介质24.然后，电容器可用于DRAM存储器件。

公开(公告)号：US07402514B2

公开(公告)日：2008-07-22

申请号：US10350451

申请日：2003-01-24

申请人： Robert Tsu ,  Joe W. McPherson ,  William R. McKee ,  Thomas Bonifield

发明人： Robert Tsu ,  Joe W. McPherson ,  William R. McKee ,  Thomas Bonifield

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76807

摘要： An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.

摘要翻译： 本发明的一个实施例是一种在第一导体和第二导体之间提供连接的方法，其中第一导体位于第二导体下方并由第一绝缘层分开，该方法包括以下步骤：在 第一绝缘层（图1-4的层124或128），开口具有顶部，底部和侧壁，并且位于第一导体和第二导体之间; 仅在开口的侧壁上形成第二绝缘层（图3和4的层134,138和142），从而在第一绝缘层中留下较小的开口; 在较小的开口中形成导电材料（图3和图4的材料140） 并且其中所述第一绝缘层由低k材料构成，并且所述第二绝缘层由具有小于所述第一绝缘层的漏电特性的漏电特性的绝缘体构成。

公开(公告)号：US6037207A

公开(公告)日：2000-03-14

申请号：US968586

申请日：1997-11-13

申请人： Isamu Asano ,  Robert Tsu

发明人： Isamu Asano ,  Robert Tsu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。

公开(公告)号：US06696337B2

公开(公告)日：2004-02-24

申请号：US10166013

申请日：2002-06-11

申请人： Isamu Asano ,  Robert Tsu

发明人： Isamu Asano ,  Robert Tsu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。

公开(公告)号：US06294420B1

公开(公告)日：2001-09-25

申请号：US09014724

申请日：1998-01-28

申请人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

发明人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L21/28518 ,  H01L21/76897 ,  H01L28/55 ,  H01L28/90

摘要： The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.

摘要翻译： 本发明公开了一种新颖的集成电路电容器及其形成方法。 电容器形成从邻近绝缘区域26的基极18开始。该基极18可以包括多晶硅或金属。 诸如硅化金属的第一材料的层28形成在基极电极18上以及相邻的绝缘区域上。 然后可以通过使第一材料28与基底电极18反应并从绝缘区域26去除第一材料28的未反应部分来形成自对准电容器电极12.然后通过在电容器电极12上形成介电层16来完成电容器 自对准电容器电极12和在电介质层16上的第二电容器电极14。

公开(公告)号：US5731220A

公开(公告)日：1998-03-24

申请号：US474614

申请日：1995-06-07

申请人： Robert Tsu ,  Bernard M. Kulwicki

发明人： Robert Tsu ,  Bernard M. Kulwicki

IPC分类号： C04B35/46 ,  H01B3/12 ,  H01L21/02 ,  H01L21/70

CPC分类号： H01L28/56 ,  H01L28/55

摘要： A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of erbium dopant (1 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size. including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without erbium precipitation than are observed for bulk BST. For erbium doping levels generally between 1% and 3%, over an order of magnitude decrease in leakage current (compared to undoped BST) may be achieved for such films.

摘要翻译： 公开了一种半导体器件及其制造方法，其将相对较大百分比的铒掺杂剂（1至5％）掺入具有小晶粒尺寸（例如10nm至50nm）的BST电介质膜24中。 电介质膜24优选地设置在电极18和26（其优选地具有接触BST的Pt层）之间，以形成具有相对高的介电常数和相对低的漏电流的电容结构。 显然，薄膜沉积的性质和晶粒尺寸小。 包括远低于体积BST烧结温度的温度，允许薄膜支持显着更高的缺陷浓度，而不会比块BST观察到的铒沉淀。 对于通常在1％和3％之间的铒掺杂水平，对于这种膜，可以实现一个数量级的漏电流下降（与未掺杂的BST相比）。