摘要:
A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.
摘要:
The invention resides in a computer-aided design system for defining physical placement and floor-planning of electronic circuits on a given substrate. Improve utilization of substrate area is achieved by arranging circuits into structural (e.g., data-path) and non-structural (e.g., non-data-path) zones for effectively segregated chip or board lay-out. Software is provided to receive a netlist file and determine therefrom which components are categorizable within structural portion. Furthermore, software is provided to produce a lay-out file which defines physical placement of the prototype design, wherein structural components are inter-placed with related control components, for example, to provide sliced-structure placement of a semiconductor chip.
摘要:
A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.