公开(公告)号：US07116718B2

公开(公告)日：2006-10-03

申请号：US10242320

申请日：2002-09-11

申请人： Qiong Wu ,  Kwok K. Chau ,  Hau-Yung Chen

发明人： Qiong Wu ,  Kwok K. Chau ,  Hau-Yung Chen

IPC分类号： H04N7/12

CPC分类号： H04N19/423 ,  H04N19/433 ,  H04N19/90

摘要： A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.

摘要翻译： 提供一种用于产生用于解码MPEG视频数据的各种二进制地址的方法和装置。 一个或多个n位计数器和多路复用器用于生成这样的二进制地址。 通过交换n位计数器的位，可以通过相同的n位计数器产生不同的二进制地址。 n位计数器可以生成的不同二进制地址的数量是n阶乘。

公开(公告)号：US5596369A

公开(公告)日：1997-01-21

申请号：US377160

申请日：1995-01-24

申请人： Kwok K. Chau

发明人： Kwok K. Chau

IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/50

CPC分类号： H04N19/42 ,  H04N19/61

摘要： A Motion Picture Experts Group (MPEG) video/audio data bitstream includes macroblocks of video data which can each include input Motion Compensation (M) data and input discrete cosine Transform Coded (I) data. A motion pipeline processes the input M data to produce processed M data, and a transform pipeline processes the input I data to produce processed I data. A controller controls the motion pipeline and the transform pipeline to concurrently process the input M data and the input I data respectively such that a length of time required for processing each macroblock is variable and is determined by the largest of a length of time required for the motion pipeline to process the input M data and a length of time required for the transform pipeline to process the input I data of the macroblock. The time required to process all of the macroblocks in a video picture is statistically less than if a fixed length of time were provided for processing each macroblock based on a worst case scenario, thereby reducing the memory bandwidth requirement of the system.

摘要翻译： 运动图像专家组（MPEG）视频/音频数据比特流包括视频数据的宏块，每个宏块可以包括输入运动补偿（M）数据和输入离散余弦变换编码（I）数据。 运动流水线处理输入M数据以产生经处理的M数据，并且变换流水线处理输入的I数据以产生经处理的I数据。 控制器控制运动管线和变换流水线，以分别同时处理输入M数据和输入I数据，使得处理每个宏块所需的时间长度是可变的，并且由所需的时间长度确定 运动管线来处理输入M数据和变换流水线处理宏块的输入I数据所需的时间长度。 在视频图像中处理所有宏块所需的时间在统计上小于根据最坏情况情况提供处理每个宏块的固定长度的时间，从而减少系统的存储器带宽需求。

公开(公告)号：US06643329B1

公开(公告)日：2003-11-04

申请号：US09636390

申请日：2000-08-09

申请人： Qiong Wu ,  Kwok K. Chau ,  Toshiaki Yoshino

发明人： Qiong Wu ,  Kwok K. Chau ,  Toshiaki Yoshino

IPC分类号： H04N712

CPC分类号： H04N19/423 ,  H04N19/61

摘要： A decoder is disclosed that provides dynamic pipelining of an incoming compressed bitstream. The decoder includes decoding logic modules capable of decoding an incoming compressed bitstream, and memory storing logic in communication with at least one of the decoding modules. Preferably, the memory storing logic is capable of determining whether a memory operation is complete that stores the uncompressed video data to memory. In addition, the decoder includes halting logic in communication with the decoding logic and the memory storing logic. The halting logic halts the decoding of the incoming bitstream during a specific time period, which includes a time period wherein the memory operation is incomplete. Finally, initiating logic is included in the decoder that is in communication with the decoding logic and the memory storing logic. The initiating logic of the decoder restarts the decoding when the memory operation is complete.

摘要翻译： 公开了提供输入压缩比特流的动态流水线的解码器。 解码器包括能够解码输入的压缩比特流的解码逻辑模块，以及与至少一个解码模块通信的存储器存储逻辑。 优选地，存储器存储逻辑能够确定存储器操作是否完成，将未压缩的视频数据存储到存储器。 此外，解码器包括停止与解码逻辑和存储器存储逻辑通信的逻辑。 停止逻辑在特定时间段期间停止对输入比特流的解码，其包括其中存储器操作不完整的时间段。 最后，起始逻辑包括在与解码逻辑和存储器存储逻辑通信的解码器中。 当存储器操作完成时，解码器的启动逻辑重新开始解码。

公开(公告)号：US5815206A

公开(公告)日：1998-09-29

申请号：US643185

申请日：1996-05-03

申请人： Srinivasa R. Malladi ,  Marc A. Miller ,  Kwok K. Chau

发明人： Srinivasa R. Malladi ,  Marc A. Miller ,  Kwok K. Chau

IPC分类号： H04B1/66 ,  H04N7/26 ,  H04N7/50 ,  H04N21/2368 ,  H04N21/434 ,  H04N7/36

CPC分类号： H04B1/665 ,  H04N19/42 ,  H04N19/61 ,  H04N21/42607 ,  H04N21/4302 ,  H04N21/434 ,  H04N21/8193

摘要： Disclosed is a partitioning procedure for designing MPEG decoders, AC-3 decoders, and decoders for other audio/video standards. The procedure provides that some specified decoding functionality be implemented exclusively in the form of hardware and certain other specified decoding functionality be provided exclusively as firmware or software. A video decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, video header processing functions; and (b) hardware for implementing preparsing assist, macroblock reconstruction, and video display control functions. An audio decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, decoding fields containing parameters for processing the audio data; and (b) hardware for implementing matrixing and windowing functions on the audio data.

摘要翻译： 公开了用于设计用于其它音频/视频标准的MPEG解码器，AC-3解码器和解码器的分区程序。 该过程规定，一些指定的解码功能仅以硬件的形式实现，并且特定的其他指定的解码功能仅作为固件或软件提供。 根据该过程设计的视频解码器包括以下元件：（a）用于结合CPU实现视频头处理功能的固件或软件; 和（b）用于实现预制辅助，宏块重构和视频显示控制功能的硬件。 根据该过程设计的音频解码器包括以下元件：（a）用于结合CPU实现包含用于处理音频数据的参数的解码字段的固件或软件; 和（b）用于在音频数据上实现矩阵和加窗功能的硬件。

公开(公告)号：US06459738B1

公开(公告)日：2002-10-01

申请号：US09494105

申请日：2000-01-28

申请人： Qiong Wu ,  Kwok K. Chau ,  Toshiaki Yoshino

发明人： Qiong Wu ,  Kwok K. Chau ,  Toshiaki Yoshino

IPC分类号： H04N712

CPC分类号： H04N19/423 ,  H04N19/61

摘要： A decoder for decoding a compressed incoming interruptible bitstream is disclosed. The decoder includes an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The decoder also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the decoder is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the decoder includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.

摘要翻译： 公开了一种用于解码压缩输入可中断比特流的解码器。 解码器包括能够接收锁存命令的输入寄存器，并且还能够在接收到锁存命令时在特定状态下锁存存储的数据。 解码器还包括与输入寄存器通信的诸如可变长度解码逻辑或游程长度解码逻辑的解码逻辑。 进一步包括在解码器中的是与解码逻辑通信的输出寄存器，其也能够接收锁存命令，并且还能够在接收到锁存命令时在特定状态下锁存存储的数据。 最后，解码器包括与输入寄存器和输出寄存器通信的寄存器控制器。 寄存器控制器能够从系统接收到停止命令，并且在接收到停止命令时，寄存器控制器将锁存命令发送到输入寄存器和输出寄存器。

公开(公告)号：US5173623A

公开(公告)日：1992-12-22

申请号：US842801

申请日：1992-02-27

申请人： Kwok K. Chau ,  James D. Gallia ,  Ashwin H. Shah

发明人： Kwok K. Chau ,  James D. Gallia ,  Ashwin H. Shah

IPC分类号： H03K19/00 ,  H03K19/0944

CPC分类号： H03K19/0008 ,  H03K19/09448

摘要： BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.

摘要翻译： 公开了BiCMOS电路，其在宽范围的负载条件下实现高速运行。 这些电路能够提供完整的输出电压摆幅并实际上消散静态功率。 BiCMOS电路使用CMOS和双极晶体管实现。 这些电路使用它们的输出信号来控制克服双极性输出下降以用于全速操作的CMOS晶体管。 可以应用相同的基本CMOS和双极配置来实现复杂和简单的逻辑功能，例如NAND，NOR，AND或OR操作。

公开(公告)号：US5163020A

公开(公告)日：1992-11-10

申请号：US685579

申请日：1991-04-15

申请人： Kwok K. Chau

发明人： Kwok K. Chau

IPC分类号： G06F7/50 ,  G06F7/507 ,  H03K19/0944

CPC分类号： G06F7/507 ,  H03K19/09448

摘要： An N-bit conditional sum adder 8 includes first and second conditional sum adders 10a and 10b. Each of the adders may be built from a plurality of one-bit conditional sum adders 110. In one embodiment, each one-bit adder 110 comprises a XNOR gate 50, a XOR gate 52, a NAND gate 54 and a NOR gate 56. The carry outputs CO.sub.a and CO.sub.b of the first conditional sum adder 10.sub.a are coupled to BiCMOS drivers 12 and 14 which in turn are coupled to the select inputs of a plurality of multiplexers 16 and 18. The multiplexers may be CMOS multiplexers built from transmission gates.

摘要翻译： N位条件和加法器8包括第一和第二条件加法器10a和10b。 每个加法器可以由多个一比特条件加法器110构建。在一个实施例中，每个一位加法器110包括XNOR门50，异或门52，与非门54和或非门56。 第一条件和加法器10a的进位输出COa和COb耦合到BiCMOS驱动器12和14，BiCMOS驱动器12和14又耦合到多个复用器16和18的选择输入。多路复用器可以是由传输门构成的CMOS多路复用器。

公开(公告)号：US5446321A

公开(公告)日：1995-08-29

申请号：US83210

申请日：1993-06-25

申请人： Toshiaki Yoshino ,  Kwok K. Chau

发明人： Toshiaki Yoshino ,  Kwok K. Chau

IPC分类号： H03K19/013 ,  H03K19/082 ,  H03K17/16

CPC分类号： H03K19/0826 ,  H03K19/0136

摘要： A tri-state driver circuit is disclosed which provides rail-to-rail output swings and does not consume a significant amount of d.c. power.

摘要翻译： 公开了一种三态驱动器电路，其提供轨至轨输出摆幅，并且不消耗大量的直流。 功率。