公开(公告)号：US20130078773A1

公开(公告)日：2013-03-28

申请号：US13576658

申请日：2011-11-22

申请人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

发明人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

IPC分类号： H01L21/8238

CPC分类号： H01L21/8238 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.

公开(公告)号：US08530302B2

公开(公告)日：2013-09-10

申请号：US13576658

申请日：2011-11-22

申请人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

发明人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

IPC分类号： H01L21/8238 ,  H01L21/4763

CPC分类号： H01L21/8238 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.

摘要翻译： 制造CMOS FET的方法包括在形成常规介电隔离之后在半导体衬底上形成第一界面SiO 2层; 形成堆叠第一高K栅极电介质/第一金属栅极; 沉积第一个硬掩模; 通过光刻和蚀刻图案化第一硬掩模; 蚀刻未被第一硬掩模覆盖的第一金属栅极和第一高K栅极电介质的部分。 然后形成第二界面SiO 2层和第二高K栅极电介质/第二金属栅极的叠层; 通过光刻和蚀刻沉积和图案化第二个硬掩模; 蚀刻未被第二硬掩模覆盖的第二金属栅极和第二高K栅极电介质的部分以露出第一金属栅极上的第一硬掩模。 通过蚀刻去除第一硬掩模和第二硬掩模; 通过光刻和蚀刻沉积多晶硅层和第三硬掩模并图案化以形成栅叠层; 沉积和蚀刻电介质层以形成第一间隔物。 然后通过常规工艺形成源极/漏极区及其延伸，并且通过硅化物形成硅化物以提供接触和金属化。

公开(公告)号：US20120115321A1

公开(公告)日：2012-05-10

申请号：US13130514

申请日：2011-02-15

申请人： Qiuxia Xu ,  Yongliang Li

发明人： Qiuxia Xu ,  Yongliang Li

IPC分类号： H01L21/28

CPC分类号： H01L21/02071 ,  H01L21/28017

摘要： The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface SiO2/high-K gate dielectric/metal gate/poly-silicon/hard mask in sequence on a silicon substrate with device isolations formed thereon; 2): forming a resist pattern by the lithography; 3): etching the gate stack structure; and 4): immersing the resultant structure of the step 3) in an etching solution to remove the polymer, wherein the etching solution consists of HF, HCl and water, the ratio of HF by volume is 0.2˜1% and the ratio of HCl by volume is 5˜15%. According to the present invention, the wet chemical etching using a mixed solution of HF and HCl is adopted and thus it is possible to completely remove the polymer remained on both sides of the gate stack and on the surface of the silicon substrate under the room temperature. According to the present invention, it is possible not only to keep a vertical etched profile of the gate stack, but also to cause no damage on the silicon substrate. The method is well compatible with the CMOS processes and is cost efficient.

摘要翻译： 本发明提供了一种在蚀刻高K栅介质/金属栅极的栅堆叠结构之后去除聚合物的方法。 该方法主要包括以下步骤：1）：在硅衬底上依次形成界面SiO 2 /高K栅极电介质/金属栅极/多晶硅/硬掩模的栅堆叠结构，其上形成器件隔离; 2）：通过光刻形成抗蚀剂图案; 3）：蚀刻栅极堆叠结构; 和4）：将所得结构的步骤3）浸入蚀刻溶液中以除去聚合物，其中蚀刻溶液由HF，HCl和水组成，HF的体积比为0.2〜1％，HCl的比例 体积为5〜15％。 根据本发明，采用使用HF和HCl的混合溶液的湿化学蚀刻，因此可以在室温下完全除去留在栅叠层两侧的聚合物和硅衬底的表面 。 根据本发明，不仅可以保持栅堆叠的垂直蚀刻轮廓，而且可以不对硅衬底造成损坏。 该方法与CMOS工艺非常兼容，具有成本效益。

公开(公告)号：US20110263114A1

公开(公告)日：2011-10-27

申请号：US13001493

申请日：2010-09-21

申请人： Yongliang Li ,  Qiuxia Xu

发明人： Yongliang Li ,  Qiuxia Xu

IPC分类号： H01L21/28

CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO2 interface layer, a high K dielectric layer, a Mo-based metal gate layer, an AlN barrier layer, a silicon gate layer and a hard mask in sequence on a semiconductor substrate; performing lithography on the semiconductor substrate with the SiO2 interface layer, the high K dielectric layer, the Mo-based metal gate layer, the AlN barrier layer, the silicon gate layer and the hard mask using a photoresist, and etching the hard mask; removing the photoresist, and performing an anisotropic etching for silicon gate with high selectivity to the underlying AlN barrier layer and metal gate by dry etching using the hard mask; performing an anisotropic etching for the AlN barrier layer, the Mo-based metal gate layer, and the high K dielectric layer by a dry etching. With the present method for etching a Mo-based metal gate stack with an aluminum nitride barrier, a vertical etching profile will be obtained and a silicon substrate has little loss, which facilities a high K dielectric/metal gate stack integration.

摘要翻译： 本申请公开了一种用氮化铝屏蔽蚀刻Mo基金属栅极叠层的方法，包括以下步骤：形成SiO 2界面层，高K电介质层，Mo基金属栅极层，AlN势垒层， 硅栅极层和硬掩模; 使用光致抗蚀剂，使用SiO 2界面层，高K电介质层，Mo基金属栅极层，AlN势垒层，硅栅极层和硬掩模在半导体衬底上进行光刻，并蚀刻硬掩模; 通过使用硬掩模的干法蚀刻，对下述AlN阻挡层和金属栅极进行高选择性的硅栅极的各向异性蚀刻; 通过干蚀刻对AlN阻挡层，Mo基金属栅极层和高K电介质层进行各向异性蚀刻。 通过本发明的用氮化铝屏障蚀刻Mo基金属栅极叠层的方法，将获得垂直蚀刻轮廓，并且硅衬底几乎没有损耗，这具有高的K电介质/金属栅堆叠集成度。

公开(公告)号：US20110256704A1

公开(公告)日：2011-10-20

申请号：US13002079

申请日：2010-09-21

申请人： Qiuxia Xu ,  Yongliang Li

发明人： Qiuxia Xu ,  Yongliang Li

IPC分类号： H01L21/3205

CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/517

摘要： A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO2 on a silicon substrate; depositing a high K dielectric film on the interfacial layer; performing a rapid thermal anneal of the high K dielectric film; depositing a TaN metal gate electrode film on the high K dielectric film; depositing a polysilicon gate layer on the TaN metal gate electrode film, and then depositing a hard mask layer; patterning a photoresist mask, and performing an anisotropic etching of the hard mask layer; removing the photoresist mask, and etching the polysilicon by reactive ion etching with the hard mask as masking layer using a mixed gas of Cl2/HBr; and etching the TaN metal gate electrode/high K dielectric gate stack by reactive ion etching with the hard mask as masking layer using BCl3-based etchant gas.

摘要翻译： 制造金属栅极/高K电介质栅叠层的方法包括以下步骤：在硅衬底上形成SiON或SiO 2的界面层; 在界面层上沉积高K电介质膜; 进行高K电介质膜的快速热退火; 在高K电介质膜上沉积TaN金属栅电极膜; 在TaN金属栅电极膜上沉积多晶硅栅极层，然后沉积硬掩模层; 图案化光致抗蚀剂掩模，并且执行硬掩模层的各向异性蚀刻; 去除光致抗蚀剂掩模，并通过使用Cl 2 / HBr的混合气体的硬掩模作为掩蔽层的反应离子蚀刻来蚀刻多晶硅; 并通过使用基于BCl3的蚀刻剂气体的硬掩模作为掩模层，通过反应离子蚀刻来蚀刻TaN金属栅极/高K电介质栅叠层。

公开(公告)号：US08163620B2

公开(公告)日：2012-04-24

申请号：US13001493

申请日：2010-09-21

申请人： Yongliang Li ,  Qiuxia Xu

发明人： Yongliang Li ,  Qiuxia Xu

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/302

CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO2 interface layer, a high K dielectric layer, a Mo-based metal gate layer, an AlN barrier layer, a silicon gate layer and a hard mask in sequence on a semiconductor substrate; performing lithography on the semiconductor substrate with the SiO2 interface layer, the high K dielectric layer, the Mo-based metal gate layer, the AlN barrier layer, the silicon gate layer and the hard mask using a photoresist, and etching the hard mask; removing the photoresist, and performing an anisotropic etching for silicon gate with high selectivity to the underlying AlN barrier layer and metal gate by dry etching using the hard mask; performing an anisotropic etching for the AlN barrier layer, the Mo-based metal gate layer, and the high K dielectric layer by a dry etching. With the present method for etching a Mo-based metal gate stack with an aluminum nitride barrier, a vertical etching profile will be obtained and a silicon substrate has little loss, which facilities a high K dielectric/metal gate stack integration.

摘要翻译： 本申请公开了一种用氮化铝屏蔽蚀刻Mo基金属栅极叠层的方法，包括以下步骤：形成SiO 2界面层，高K电介质层，Mo基金属栅极层，AlN势垒层， 硅栅极层和硬掩模; 使用光致抗蚀剂，使用SiO 2界面层，高K电介质层，Mo基金属栅极层，AlN势垒层，硅栅极层和硬掩模在半导体衬底上进行光刻，并蚀刻硬掩模; 通过使用硬掩模的干法蚀刻，对下述AlN阻挡层和金属栅极进行高选择性的硅栅极的各向异性蚀刻; 通过干蚀刻对AlN阻挡层，Mo基金属栅极层和高K电介质层进行各向异性蚀刻。 通过本发明的用氮化铝屏障蚀刻Mo基金属栅极叠层的方法，将获得垂直蚀刻轮廓，并且硅衬底几乎没有损耗，这具有高的K电介质/金属栅堆叠集成度。

公开(公告)号：US20120003827A1

公开(公告)日：2012-01-05

申请号：US13129584

申请日：2011-02-17

申请人： Qiuxia Xu ,  Yongliang Li

发明人： Qiuxia Xu ,  Yongliang Li

IPC分类号： H01L21/28

CPC分类号： H01L21/32136 ,  H01L21/02057 ,  H01L21/28088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32137 ,  H01L21/823828 ,  H01L29/4966

摘要： A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration.

摘要翻译： 一种在栅极首先工艺中制造金属栅极叠层结构的方法包括以下步骤：制备常规的LOCOS和STI隔离：通过快速热氧化或化学工艺在半导体衬底上生长氧化物或氧氮化物的非薄界面层; 在非薄界面氧化物层上沉积高介电常数（K）栅极电介质，然后进行快速热退火; 沉积TiN金属栅极; 沉积AlN或TaN的阻挡层; 沉积多晶硅膜和硬掩模，并执行光刻和硬掩模的蚀刻; 在光刻胶去除之后，依次蚀刻多晶硅/金属栅极/高K栅极电介质以形成金属栅叠层结构。 本发明的制造方法适用于纳米级CMOS器件中的高K电介质/金属栅极的集成，并且消除了实现高K /金属栅极集成的障碍物。

公开(公告)号：US08598002B2

公开(公告)日：2013-12-03

申请号：US13129584

申请日：2011-02-17

申请人： Qiuxia Xu ,  Yongliang Li

发明人： Qiuxia Xu ,  Yongliang Li

IPC分类号： H01L21/00

CPC分类号： H01L21/32136 ,  H01L21/02057 ,  H01L21/28088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32137 ,  H01L21/823828 ,  H01L29/4966

摘要： A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration.

摘要翻译： 一种在栅极首先工艺中制造金属栅极叠层结构的方法包括以下步骤：制备常规的LOCOS和STI隔离：通过快速热氧化或化学工艺在半导体衬底上生长氧化物或氧氮化物的非薄界面层; 在非薄界面氧化物层上沉积高介电常数（K）栅极电介质，然后进行快速热退火; 沉积TiN金属栅极; 沉积AlN或TaN的阻挡层; 沉积多晶硅膜和硬掩模，并执行光刻和硬掩模的蚀刻; 在光刻胶去除之后，依次蚀刻多晶硅/金属栅极/高K栅极电介质以形成金属栅叠层结构。 本发明的制造方法适用于纳米级CMOS器件中的高K电介质/金属栅极的集成，并且消除了实现高K /金属栅极集成的障碍物。

公开(公告)号：US08574977B2

公开(公告)日：2013-11-05

申请号：US13503358

申请日：2011-11-21

申请人： Qiuxia Xu ,  Yongliang Li

发明人： Qiuxia Xu ,  Yongliang Li

IPC分类号： H01L21/8238

CPC分类号： H01L21/26586 ,  H01L21/28088 ,  H01L29/4966

摘要： The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method after conventional LOCOS or STI dielectric isolation is completed; depositing high-K gate dielectric and performing rapid thermal annealing; depositing a composite metal gate; depositing a barrier metal layer; depositing a polysilicon film and a hard mask and then performing photolithography and etching the hard mask; removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface oxide layer in sequence to form a gate stack structure of polysilicon film/barrier metal layer/metal gate/high-K gate dielectric; forming spacers, source/drain implantation in a conventional manner and performing rapid thermal annealing, whereby while source/drain dopants are activated, adjusting of metal gate effective work function of the PMOS device is achieved.

摘要翻译： 本公开提供了一种用于制造栅极堆叠结构并调整PMOS器件的栅极功能的方法，包括：在常规LOCOS之后通过快速热氧化或化学方法在半导体衬底上生长超薄界面氧化物层或氧氮化物层 或STI绝缘隔离完成; 沉积高K栅介质并进行快速热退火; 沉积复合金属门; 沉积阻挡金属层; 沉积多晶硅膜和硬掩模，然后进行光刻和蚀刻硬掩模; 去除光致抗蚀剂并依次蚀刻多晶硅膜，阻挡金属层，金属栅极，高K栅极电介质和界面氧化物层，以形成多晶硅膜/阻挡金属层/金属栅极/ K栅电介质; 以常规方式形成间隔物，源极/漏极注入并执行快速热退火，由此在源极/漏极掺杂剂被激活时，实现了PMOS器件的金属栅极有效功函数的调整。

公开(公告)号：US08334205B2

公开(公告)日：2012-12-18

申请号：US13130514

申请日：2011-02-15

申请人： Qiuxia Xu ,  Yongliang Li

发明人： Qiuxia Xu ,  Yongliang Li

IPC分类号： H01L21/44

CPC分类号： H01L21/02071 ,  H01L21/28017

摘要： The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface Si2/high-K gate dielectric/metal gate/poly-silicon/hard mask in sequence on a silicon substrate with device isolations formed thereon; 2): forming a resist pattern by the lithography; 3): etching the gate stack structure; and 4): immersing the resultant structure of the step 3) in an etching solution to remove the polymer, wherein the etching solution consists of HF, HCl and water, the ratio of HF by volume is 0.2˜1% and the ratio of HCl by volume is 5˜15%.

摘要翻译： 本发明提供了一种在蚀刻高K栅介质/金属栅极的栅堆叠结构之后去除聚合物的方法。 该方法主要包括以下步骤：1）在硅衬底上依次形成界面Si2 /高K栅极电介质/金属栅极/多晶硅/硬掩模的栅堆叠结构，其上形成器件隔离; 2）：通过光刻形成抗蚀剂图案; 3）：蚀刻栅极堆叠结构; 和4）：将所得结构的步骤3）浸入蚀刻溶液中以除去聚合物，其中蚀刻溶液由HF，HCl和水组成，HF的体积比为0.2〜1％，HCl的比例 体积为5〜15％。