公开(公告)号：US20230305971A1

公开(公告)日：2023-09-28

申请号：US17650455

申请日：2022-02-09

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

公开(公告)号：US12038855B2

公开(公告)日：2024-07-16

申请号：US17650455

申请日：2022-02-09

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

公开(公告)号：US11175836B2

公开(公告)日：2021-11-16

申请号：US16803977

申请日：2020-02-27

Applicant: Qualcomm Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor ,  Ravindra Kumar

IPC: G06F3/06 ,  G06F12/0875

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

公开(公告)号：US20240176751A1

公开(公告)日：2024-05-30

申请号：US18059937

申请日：2022-11-29

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/1642 ,  G06F13/1673

Abstract: This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

公开(公告)号：US20240311317A1

公开(公告)日：2024-09-19

申请号：US18674138

申请日：2024-05-24

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

公开(公告)号：US11907141B1

公开(公告)日：2024-02-20

申请号：US17929946

申请日：2022-09-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Subbarao Palacharla

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F13/1694 ,  G06F12/0623

Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

公开(公告)号：US11360897B1

公开(公告)日：2022-06-14

申请号：US17231867

申请日：2021-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor

IPC: G06F12/0831 ,  G06F12/0864 ,  G06F13/40 ,  G06F13/16 ,  G06F12/02

Abstract: Dynamic random access memory (DRAM) data may be accessed by a memory controller using a broadcast mode or a non-broadcast mode. In the broadcast mode, a first portion of data that is the subject of an access request and a second portion of the data that is the subject of the access request may be accessed concurrently via first and second pseudo-channels, respectively. In the non-broadcast mode, data that is the subject of the access request may be accessed via a selected one of the first and second pseudo-channels.

公开(公告)号：US20200278802A1

公开(公告)日：2020-09-03

申请号：US16803977

申请日：2020-02-27

Applicant: Qualcomm Incorporated

Inventor： Jungwon SUH ,  Dexter Tamio Chun ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor ,  Ravindra Kumar

IPC: G06F3/06 ,  G06F12/0875

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

公开(公告)号：US12153531B2

公开(公告)日：2024-11-26

申请号：US18059937

申请日：2022-11-29

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

Abstract: This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

公开(公告)号：US11893240B2

公开(公告)日：2024-02-06

申请号：US17452606

申请日：2021-10-28

Applicant: QUALCOMM Incorporated

Inventor： Shyamkumar Thoziyoor ,  Pankaj Deshmukh ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0635 ,  G06F3/0679

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.