公开(公告)号：US12188870B2

公开(公告)日：2025-01-07

申请号：US17224925

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: H01L27/146 ,  G01N21/64 ,  G05F1/46

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US20230152229A1

公开(公告)日：2023-05-18

申请号：US18093213

申请日：2023-01-04

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64 ,  G05F1/46 ,  H01L27/146

CPC classification number: G01N21/6456 ,  G05F1/46 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14643 ,  G01N21/6408 ,  G01N21/6454 ,  H01L27/14603 ,  H01L27/14614 ,  G01N2021/6439

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US11573180B2

公开(公告)日：2023-02-07

申请号：US17224899

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64 ,  G05F1/46 ,  H01L27/146

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US20210318238A1

公开(公告)日：2021-10-14

申请号：US17224925

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US12092579B2

公开(公告)日：2024-09-17

申请号：US18093213

申请日：2023-01-04

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64 ,  G05F1/46 ,  H01L27/146

CPC classification number: G01N21/6456 ,  G01N21/6408 ,  G01N21/6454 ,  G05F1/46 ,  H01L27/14603 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14643 ,  G01N2021/6439

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US20210318242A1

公开(公告)日：2021-10-14

申请号：US17224899

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64 ,  G05F1/46 ,  H01L27/146

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.