公开(公告)号：US11719639B2

公开(公告)日：2023-08-08

申请号：US17190331

申请日：2021-03-02

申请人： Quantum-Si Incorporated

发明人： Gerard Schmid ,  Dajiang Yang ,  Eric A. G. Webster ,  Xin Wang ,  Todd Rearick ,  Changhoon Choi ,  Ali Kabiri ,  Kyle Preston ,  Brian Reed

IPC分类号： G01N21/64 ,  H01L27/146

CPC分类号： G01N21/6454 ,  G01N21/6408 ,  G01N21/6428 ,  H01L27/14603 ,  G01N2021/6463

摘要： Some aspects relate to an integrated circuit, comprising at least one photodetection region configured to generate charge carriers responsive to incident photons emitted from a sample, at least one charge storage region configured to receive the charge carriers from the photodetection region, and at least one controller configured to obtain information about the incident photons, the information comprising at least one member selected from the group comprising pulse duration and interpulse duration and at least one member selected from the group comprising wavelength information, luminescence lifetime information, and intensity information. In some embodiments, the information comprises at least three, four, and/or five members selected from the group comprising wavelength information, luminescence lifetime information, intensity information, pulse duration information, and interpulse duration information. In some embodiments, the information obtained may be used to identify the sample.

公开(公告)号：US20230152229A1

公开(公告)日：2023-05-18

申请号：US18093213

申请日：2023-01-04

申请人： Quantum-Si Incorporated

发明人： Eric A.G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC分类号： G01N21/64 ,  G05F1/46 ,  H01L27/146

CPC分类号： G01N21/6456 ,  G05F1/46 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14643 ,  G01N21/6408 ,  G01N21/6454 ,  H01L27/14603 ,  H01L27/14614 ,  G01N2021/6439

摘要： Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US11573180B2

公开(公告)日：2023-02-07

申请号：US17224899

申请日：2021-04-07

申请人： Quantum-Si Incorporated

发明人： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC分类号： G01N21/64 ,  G05F1/46 ,  H01L27/146

摘要： Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US20210270740A1

公开(公告)日：2021-09-02

申请号：US17190331

申请日：2021-03-02

申请人： Quantum-Si Incorporated

发明人： Gerard Schmid ,  Dajiang Yang ,  Eric A.G. Webster ,  Xin Wang ,  Todd Rearick ,  Changhoon Choi ,  Ali Kabiri ,  Kyle Preston ,  Brian Reed

IPC分类号： G01N21/64

摘要： Some aspects relate to an integrated circuit, comprising at least one photodetection region configured to generate charge carriers responsive to incident photons emitted from a sample, at least one charge storage region configured to receive the charge carriers from the photodetection region, and at least one controller configured to obtain information about the incident photons, the information comprising at least one member selected from the group comprising pulse duration and interpulse duration and at least one member selected from the group comprising wavelength information, luminescence lifetime information, and intensity information. In some embodiments, the information comprises at least three, four, and/or five members selected from the group comprising wavelength information, luminescence lifetime information, intensity information, pulse duration information, and interpulse duration information. In some embodiments, the information obtained may be used to identify the sample.

公开(公告)号：US20240353326A1

公开(公告)日：2024-10-24

申请号：US18539068

申请日：2023-12-13

申请人： Quantum-Si Incorporated

发明人： Gerard Schmid ,  Dajiang Yang ,  Eric A.G. Webster ,  Xin Wang ,  Todd Rearick ,  Changhoon Choi ,  Ali Kabiri ,  Kyle Preston

IPC分类号： G01N21/64

CPC分类号： G01N21/6428 ,  G01N2021/6417 ,  G01N2021/6439

摘要： Some aspects relate to integrated devices for obtaining timing and/or spectral information from incident light. In some embodiments, a pixel may include one or more charge storage regions configured to receive charge carriers generated responsive to incident photons from a light source, with charge carriers stored in the charge storage region(s) indicative of spectral and timing information. In some embodiments, a pixel may include regions having different depths, each configured to generate charge carriers responsive to incident photons. In some embodiments, a pixel may include multiple charge storage regions having different depths, and one or more of the charge storage regions may be configured to receive the incident photons and generate charge carriers therein. In some embodiments, a pixel may include an optical sorting element configured to direct at least some incident photons to one charge storage region and other incident photons to another charge storage region.

公开(公告)号：US12092579B2

公开(公告)日：2024-09-17

申请号：US18093213

申请日：2023-01-04

申请人： Quantum-Si Incorporated

发明人： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC分类号： G01N21/64 ,  G05F1/46 ,  H01L27/146

CPC分类号： G01N21/6456 ,  G01N21/6408 ,  G01N21/6454 ,  G05F1/46 ,  H01L27/14603 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14643 ,  G01N2021/6439

摘要： Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US11869917B2

公开(公告)日：2024-01-09

申请号：US17149574

申请日：2021-01-14

申请人： Quantum-Si Incorporated

发明人： Eric A. G. Webster ,  Changhoon Choi ,  Dajiang Yang ,  Xin Wang ,  Todd Rearick ,  Kyle Preston ,  Ali Kabiri ,  Gerard Schmid

IPC分类号： H01L27/146

CPC分类号： H01L27/14643 ,  H01L27/14683

摘要： Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, a charge storage region and the drain region may be positioned on a same side of the photodetection region. In some embodiments, at least one drain layer may be configured to receive incident photons and/or charge carriers via the photodetection region. In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in the plurality of pixels.

公开(公告)号：US11804499B2

公开(公告)日：2023-10-31

申请号：US16913688

申请日：2020-06-26

申请人： Quantum-Si Incorporated

发明人： Dajiang Yang ,  Farshid Ghasemi ,  Keith G. Fife ,  Todd Rearick ,  Ali Kabiri ,  Gerard Schmid ,  Eric A. G. Webster

IPC分类号： H01L27/146 ,  H04N25/771

CPC分类号： H01L27/14609 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14636 ,  H04N25/771

摘要： Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.

公开(公告)号：US20230253421A1

公开(公告)日：2023-08-10

申请号：US18133489

申请日：2023-04-11

申请人： Quantum-Si Incorporated

发明人： Dajiang Yang ,  Farshid Ghasemi ,  Keith G. Fife ,  Todd Rearick ,  Ali Kabiri ,  Gerard Schmidt ,  Eric A.G. Webster

IPC分类号： H01L27/146

CPC分类号： H01L27/14609 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14623 ,  H04N25/771

摘要： Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.

公开(公告)号：US20210318242A1

公开(公告)日：2021-10-14

申请号：US17224899

申请日：2021-04-07

申请人： Quantum-Si Incorporated

发明人： Eric A.G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC分类号： G01N21/64 ,  G05F1/46 ,  H01L27/146

摘要： Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.