公开(公告)号：US12085442B2

公开(公告)日：2024-09-10

申请号：US17507585

申请日：2021-10-21

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Todd Rearick ,  Thomas Raymond Thurston

IPC: G01J1/44 ,  B01J19/00 ,  H01L27/146 ,  H01L27/148

CPC classification number: G01J1/44 ,  B01J19/0046 ,  H01L27/14683 ,  H01L27/14818 ,  H01L27/14825 ,  B01J2219/00504 ,  B01J2219/00576 ,  B01J2219/00587 ,  B01J2219/00689 ,  B01J2219/00698 ,  G01J2001/446

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

公开(公告)号：US11714001B2

公开(公告)日：2023-08-01

申请号：US17507596

申请日：2021-10-21

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Todd Rearick ,  Thomas Raymond Thurston

IPC: G01J1/44 ,  H01L27/148 ,  B01J19/00 ,  H01L27/146

CPC classification number: G01J1/44 ,  B01J19/0046 ,  H01L27/14683 ,  H01L27/14818 ,  H01L27/14825 ,  B01J2219/00504 ,  B01J2219/00576 ,  B01J2219/00587 ,  B01J2219/00689 ,  B01J2219/00698 ,  G01J2001/446

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

公开(公告)号：US11573180B2

公开(公告)日：2023-02-07

申请号：US17224899

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64 ,  G05F1/46 ,  H01L27/146

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US12203855B2

公开(公告)日：2025-01-21

申请号：US18539068

申请日：2023-12-13

Applicant: Quantum-Si Incorporated

Inventor： Gerard Schmid ,  Dajiang Yang ,  Eric A. G. Webster ,  Xin Wang ,  Todd Rearick ,  Changhoon Choi ,  Ali Kabiri ,  Kyle Preston

IPC: G01N21/64

Abstract: Some aspects relate to integrated devices for obtaining timing and/or spectral information from incident light. In some embodiments, a pixel may include one or more charge storage regions configured to receive charge carriers generated responsive to incident photons from a light source, with charge carriers stored in the charge storage region(s) indicative of spectral and timing information. In some embodiments, a pixel may include regions having different depths, each configured to generate charge carriers responsive to incident photons. In some embodiments, a pixel may include multiple charge storage regions having different depths, and one or more of the charge storage regions may be configured to receive the incident photons and generate charge carriers therein. In some embodiments, a pixel may include an optical sorting element configured to direct at least some incident photons to one charge storage region and other incident photons to another charge storage region.

公开(公告)号：US12169142B2

公开(公告)日：2024-12-17

申请号：US18489841

申请日：2023-10-18

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Todd Rearick ,  Thomas Raymond Thurston

IPC: G01J1/44 ,  B01J19/00 ,  H01L27/146 ,  H01L27/148

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

公开(公告)号：US12159887B2

公开(公告)日：2024-12-03

申请号：US18452235

申请日：2023-08-18

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster

IPC: H01L27/146 ,  G01N21/64

Abstract: In some embodiments, an integrated circuit includes multiple charge storage regions configured to receive charge carriers from a photodetection region in response to a single excitation of a sample. In some embodiments, an integrated circuit includes first and second charge transfer paths configured to electrically couple a photodetection region to first and second charge storage regions, with the second charge transfer path bypassing the first charge storage region. In some embodiments, an integrated circuit includes a photodetection region configured to induce an intrinsic electric field having a vector component in at least three substantially perpendicular directions. In some embodiments, an integrated circuit includes multiple transfer gates configured to control charge carrier transfer out of a photodetection region in different directions. In some embodiments, an integrated circuit includes a photodetection region and multiple transfer gates configured to control charge carrier transfer from the photodetection region to one or more drain regions.

公开(公告)号：US11885744B2

公开(公告)日：2024-01-30

申请号：US17149310

申请日：2021-01-14

Applicant: Quantum-Si Incorporated

Inventor： Gerard Schmid ,  Dajiang Yang ,  Eric A. G. Webster ,  Xin Wang ,  Todd Rearick ,  Changhoon Choi ,  Ali Kabiri ,  Kyle Preston

IPC: G01N21/64

CPC classification number: G01N21/6428 ,  G01N2021/6417 ,  G01N2021/6439

Abstract: Some aspects relate to integrated devices for obtaining timing and/or spectral information from incident light. In some embodiments, a pixel may include one or more charge storage regions configured to receive charge carriers generated responsive to incident photons from a light source, with charge carriers stored in the charge storage region(s) indicative of spectral and timing information. In some embodiments, a pixel may include regions having different depths, each configured to generate charge carriers responsive to incident photons. In some embodiments, a pixel may include multiple charge storage regions having different depths, and one or more of the charge storage regions may be configured to receive the incident photons and generate charge carriers therein. In some embodiments, a pixel may include an optical sorting element configured to direct at least some incident photons to one charge storage region and other incident photons to another charge storage region.

公开(公告)号：US12188870B2

公开(公告)日：2025-01-07

申请号：US17224925

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: H01L27/146 ,  G01N21/64 ,  G05F1/46

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US11719639B2

公开(公告)日：2023-08-08

申请号：US17190331

申请日：2021-03-02

Applicant: Quantum-Si Incorporated

Inventor： Gerard Schmid ,  Dajiang Yang ,  Eric A. G. Webster ,  Xin Wang ,  Todd Rearick ,  Changhoon Choi ,  Ali Kabiri ,  Kyle Preston ,  Brian Reed

IPC: G01N21/64 ,  H01L27/146

CPC classification number: G01N21/6454 ,  G01N21/6408 ,  G01N21/6428 ,  H01L27/14603 ,  G01N2021/6463

Abstract: Some aspects relate to an integrated circuit, comprising at least one photodetection region configured to generate charge carriers responsive to incident photons emitted from a sample, at least one charge storage region configured to receive the charge carriers from the photodetection region, and at least one controller configured to obtain information about the incident photons, the information comprising at least one member selected from the group comprising pulse duration and interpulse duration and at least one member selected from the group comprising wavelength information, luminescence lifetime information, and intensity information. In some embodiments, the information comprises at least three, four, and/or five members selected from the group comprising wavelength information, luminescence lifetime information, intensity information, pulse duration information, and interpulse duration information. In some embodiments, the information obtained may be used to identify the sample.

公开(公告)号：US12297496B2

公开(公告)日：2025-05-13

申请号：US17548428

申请日：2021-12-10

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster

IPC: C12Q1/6869 ,  G01N21/64 ,  H01L27/146 ,  H01L27/148 ,  H01S3/1112

Abstract: The present disclosure provides techniques for improving the rate and efficiency of charge transfer within an integrated circuit configured to receive incident photons. Some aspects of the present disclosure relate to integrated circuits that are configured to induce one or more intrinsic electric fields that increase the rate and efficiency of charge transfer within the integrated circuits. Some aspects of the present disclosure relate to integrated circuits configured to induce a charge carrier depletion in the photodetection region(s) of the integrated circuits. In some embodiments, the charge carrier depletion in the photodetection region(s) may be intrinsic, in that the depletion is induced even in the absence of external electric fields applied to the integrated circuit. Some aspects of the present disclosure relate to processes for operating and/or manufacturing integrated devices as described herein.