公开(公告)号：US20030115553A1

公开(公告)日：2003-06-19

申请号：US10022776

申请日：2001-12-13

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  W. James Scheuermann

IPC: G06F017/50

CPC classification number: G06F9/30189 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/325

Abstract: A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

Abstract translation: 一种微处理器架构，包括与用于执行微指令的微代码指令高速缓存组合的有限状态机。 通常会导致高重复循环操作的小序列的微指令在有限状态机（FSM）中实现。 使用FSM比缓存或寄存器集中的循环指令更节能。 此外，在执行微代码指令时，缓存或其他面向内存的方法的灵活性仍然可用。 通过ID标签将微指令识别为FSM操作（与高速缓存操作相反）。 微指令的其他领域可用于识别要使用的FSM电路的类型，直接配置FSM以实现微指令，指示某些字段将在一个或多个FSM和/或面向内存的操作中实现，例如 如缓存或注册。

公开(公告)号：US20040025159A1

公开(公告)日：2004-02-05

申请号：US10443501

申请日：2003-05-21

Applicant: QuickSilver Technology, Inc.

Inventor： W. James Scheuermann ,  Eugene B. Hogenauer

IPC: G06F009/00

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/4881 ,  G06F9/52 ,  G06F13/28 ,  G06F15/17331

Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or nullunits,null are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.

Abstract translation: 用于管理自适应计算系统中的操作的硬件任务管理器。 任务管理器指示输入和输出缓冲区资源何时足以允许任务执行。 该任务可能需要来自一个或多个其他（或相同）任务的任意数量的输入值。 同样，在任务可以开始执行并将结果存储在输出缓冲区之前，还必须有许多输出缓冲区可用。 硬件任务管理器维护与每个输入和输出缓冲器相关联的计数器。 对于输入缓冲器，计数器的负值表示缓冲器中没有数据，因此相应的输入缓冲器尚未就绪或可用。 因此，相关任务无法运行。 预定的字节数或“单位”被存储到输入缓冲器中，相关联的计数器递增。 当计数器值从负值转换为零时，计数器的高位被清除，从而指示输入缓冲器具有足够的数据，并可由任务处理。

公开(公告)号：US20040078403A1

公开(公告)日：2004-04-22

申请号：US10386896

申请日：2003-03-11

Applicant: QuickSilver Technology, Inc.

Inventor： W. James Scheuermann ,  Otis Lamont Frost III

IPC: G06F017/10

CPC classification number: H03H17/0294 ,  H03H21/0012

Abstract: A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.

Abstract translation: 一种可重构滤波器节点，包括适于存储多个输入数据值的输入数据存储器，适于存储多个滤波器系数值的滤波器系数存储器，以及适于同时计算滤波器数据值的多个计算单元。 滤波器数据值是响应于输入数据值的滤波器的输出或将在随后的滤波数据值计算中使用的第二多个滤波器系数。 第一和第二输入数据寄存器加载连续的输入数据值输入数据存储器或从相邻的计算单元加载。 每个计算单元包括预加法器，其适于输出存储在计算单元中的和两个输入数据值，或者交替地输出单个输入数据值，以及乘法和累加单元， 加法器通过滤波器系数并累加结果。

公开(公告)号：US20040030736A1

公开(公告)日：2004-02-12

申请号：US10443596

申请日：2003-05-21

Applicant: QuickSilver Technology, Inc.

Inventor： W. James Scheuermann

IPC: G06F017/14

CPC classification number: G06F15/7867

Abstract: A computational unit, or node, in an adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric FIR Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad IIR Filter, Radix-2 FFT/IFFT, Radix-2 DCT/IDCT, Golay Correlator, Local Oscillator/Mixer.

Abstract translation: 描述了可适应性计算系统中的计算单元或节点。 节点的优选实施例允许通过使用具有可配置互连方案的执行单元的组合来适配用于十种类型的功能中的任何一种的节点。 功能类型包括：不对称FIR滤波器，对称FIR滤波器，复乘数FIR滤波器，绝对差值和双线性插值，二维IIR滤波器，二进制FFT / IFFT，二进制DCT / IDCT ，Golay相关器，本地振荡器/混频器。

公开(公告)号：US20040010645A1

公开(公告)日：2004-01-15

申请号：US10443554

申请日：2003-05-21

Applicant: QuickSilver Technology, Inc.

Inventor： W. James Scheuermann ,  Eugene B. Hogenauer

IPC: G06F013/00

CPC classification number: G06F9/4494

Abstract: A computational unit, or node, in an adaptive computing engine uses a uniform interface to a network to communicate with other nodes and resources. The uniform interface is referred to as a nullnode wrapper.null The node wrapper includes a hardware task manager (HTM), a data distributor, optional direct memory access (DMA) engine and a data aggregator. The hardware task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The HTM coordinates a nodes assigned tasks using a task lists. A nullready-to-run queuenull is implemented as a first-in first-out stack. The HTM uses a top-level finite-state machine (FSM) that communicates with a number of subordinate FSMs to control individual HTM components. The Data Distributor interfaces between the node's input pipeline register and various memories and registers within the node. Different types of data distribution are possible based upon the values in service and auxiliary fields of a 50-bit control structure. The Data Aggregator arbitrates among up to four node elements that request access to the node's output pipeline register for the purpose of transferring data to the intended destination via the network. The DMA Engine uses a five-register model. The registers include a Starting Address Register, an Address Stride Register, a Transfer Count Register, a Duty Cycle Register, and a Control Register including a GO bit, Target Node number/port number, and DONE protocol. A control node, or nullK-node,null is used to control various aspects of the HTM, data distributor, data aggregator and DMA operations within the nodes of the system.

Abstract translation: 自适应计算引擎中的计算单元或节点使用与网络的统一接口与其他节点和资源进行通信。 统一接口被称为“节点包装器”。 节点包装器包括硬件任务管理器（HTM），数据分配器，可选的直接存储器访问（DMA）引擎和数据聚合器。 硬件任务管理器指示输入和输出缓冲区资源何时足以允许任务执行。 HTM使用任务列表协调节点分配的任务。 “即时运行队列”作为先进先出的堆栈实现。 HTM使用与许多从属FSM通信的顶级有限状态机（FSM）来控制各个HTM组件。 数据分发器在节点的输入流水线寄存器与节点内的各种存储器和寄存器之间进行接口。 基于50位控制结构的服务和辅助字段的值，可以实现不同类型的数据分发。 数据聚合器在最多四个节点元素之间进行仲裁，这些元素要求访问节点的输出流水线寄存器，以便通过网络将数据传输到预期的目的地。 DMA引擎使用五注册模型。 这些寄存器包括起始地址寄存器，地址步进寄存器，传输计数寄存器，占空比寄存器和包含GO位，目标节点号/端口号和DONE协议的控制寄存器。 控制节点或“K节点”用于控制系统节点内的HTM，数据分发器，数据聚合器和DMA操作的各个方面。