公开(公告)号：US20020161568A1

公开(公告)日：2002-10-31

申请号：US09922113

申请日：2001-08-02

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Mikhail Bershteyn ,  Michael R. Butts ,  Jerry R. Bauer

IPC: G06F009/455

CPC classification number: G01R31/2853 ,  G01R31/31717 ,  G06F17/5027 ,  Y10S370/916

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract translation: 公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。 本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。 逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板迹线。 还公开了一种用于硬件仿真系统的逻辑分析仪。 执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。

公开(公告)号：US20030074178A1

公开(公告)日：2003-04-17

申请号：US10128178

申请日：2002-04-22

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Mikhail Bershteyn ,  Michael R. Butts ,  Jerry R. Bauer

IPC: G06F009/455

CPC classification number: G01R31/2853 ,  G01R31/31717 ,  G06F17/5027 ,  Y10S370/916

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract translation: 公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。 本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。 逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板迹线。 还公开了一种用于硬件仿真系统的逻辑分析仪。 执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。