公开(公告)号：US20020161568A1

公开(公告)日：2002-10-31

申请号：US09922113

申请日：2001-08-02

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Mikhail Bershteyn ,  Michael R. Butts ,  Jerry R. Bauer

IPC: G06F009/455

CPC classification number: G01R31/2853 ,  G01R31/31717 ,  G06F17/5027 ,  Y10S370/916

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract translation: 公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。 本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。 逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板迹线。 还公开了一种用于硬件仿真系统的逻辑分析仪。 执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。

公开(公告)号：US20020095649A1

公开(公告)日：2002-07-18

申请号：US09949006

申请日：2001-09-06

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Michael R. Butts

IPC: G06F017/50

CPC classification number: H03K19/17736 ,  G06F15/7867 ,  G06F17/5027

Abstract: A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic

Abstract translation: 用于集成电路仿真和原型设计的逻辑芯片。 逻辑芯片包括多个逻辑元件，其被分成多个逻辑元件子集。 逻辑芯片还包括多个第一级互连。 多个第一级互连互连多个逻辑元件子集中的一个，从而形成多个第一级逻辑单元。 多个第一级逻辑单元被分成多个第一级逻辑单元子集。 逻辑芯片还包括多个第二级互连。 第二级互连将第一级逻辑单元的多个子集中的一个互连，从而形成多个第二级逻辑单元。 逻辑芯片还包括第三级互连。 第三级互连将多个第二级逻辑单元互连，从而形成第三级逻辑

公开(公告)号：US20040123258A1

公开(公告)日：2004-06-24

申请号：US10669095

申请日：2003-09-23

Applicant: Quickturn Design Systems, Inc.

Inventor： Michael R. Butts

IPC: G06F017/50

CPC classification number: G06F17/5027

Abstract: A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.

Abstract translation: 公开了一种使用具有不同数量的逻辑处理器，宏处理器，存储器处理器和其中编程的通用处理器的可编程逻辑器件的设计验证系统。 这些各种处理器可以执行布尔函数，宏操作，存储器操作和其他计算机指令。 这避免了实现逻辑的需要或将逻辑处理器的设计编入许多门级布尔逻辑运算的需要。 在验证某些类型的设计时，会以更低的成本，更低的功率和/或更高的速度的形式提高效率。

公开(公告)号：US20030154458A1

公开(公告)日：2003-08-14

申请号：US10356919

申请日：2003-01-30

Applicant: Quickturn Design Systems, Inc.

Inventor： Michael R. Butts ,  Ming Yang Wang ,  Swey-Yan Shei ,  Alon Kfir

IPC: G06F017/50

CPC classification number: G06F17/5027

Abstract: A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

公开(公告)号：US20030074178A1

公开(公告)日：2003-04-17

申请号：US10128178

申请日：2002-04-22

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Mikhail Bershteyn ,  Michael R. Butts ,  Jerry R. Bauer

IPC: G06F009/455

CPC classification number: G01R31/2853 ,  G01R31/31717 ,  G06F17/5027 ,  Y10S370/916

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract translation: 公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。 本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。 逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板迹线。 还公开了一种用于硬件仿真系统的逻辑分析仪。 执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。