公开(公告)号：US20020107682A1

公开(公告)日：2002-08-08

申请号：US10107741

申请日：2002-03-26

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Michael R. D'Amour ,  Thomas S. Payne

IPC: G06F009/455

CPC classification number: G06F11/261 ,  G06F17/5027

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Abstract translation: 用于电子电路或系统的物理仿真的系统包括数据输入工作站，其中用户可以输入表示电路或系统配置的数据。 该数据被转换成适合于编程具有丰富互连架构的可编程门元件阵列的形式。 规定用于外部连接VLSI设备或用户电路或系统的其他部分。 通过利用可编程门阵列中未使用的电路路径可以获得内部探测互连网络。

公开(公告)号：US20020161568A1

公开(公告)日：2002-10-31

申请号：US09922113

申请日：2001-08-02

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Mikhail Bershteyn ,  Michael R. Butts ,  Jerry R. Bauer

IPC: G06F009/455

CPC classification number: G01R31/2853 ,  G01R31/31717 ,  G06F17/5027 ,  Y10S370/916

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract translation: 公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。 本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。 逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板迹线。 还公开了一种用于硬件仿真系统的逻辑分析仪。 执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。

公开(公告)号：US20020095649A1

公开(公告)日：2002-07-18

申请号：US09949006

申请日：2001-09-06

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Michael R. Butts

IPC: G06F017/50

CPC classification number: H03K19/17736 ,  G06F15/7867 ,  G06F17/5027

Abstract: A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic

Abstract translation: 用于集成电路仿真和原型设计的逻辑芯片。 逻辑芯片包括多个逻辑元件，其被分成多个逻辑元件子集。 逻辑芯片还包括多个第一级互连。 多个第一级互连互连多个逻辑元件子集中的一个，从而形成多个第一级逻辑单元。 多个第一级逻辑单元被分成多个第一级逻辑单元子集。 逻辑芯片还包括多个第二级互连。 第二级互连将第一级逻辑单元的多个子集中的一个互连，从而形成多个第二级逻辑单元。 逻辑芯片还包括第三级互连。 第三级互连将多个第二级逻辑单元互连，从而形成第三级逻辑

公开(公告)号：US20030074178A1

公开(公告)日：2003-04-17

申请号：US10128178

申请日：2002-04-22

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Mikhail Bershteyn ,  Michael R. Butts ,  Jerry R. Bauer

IPC: G06F009/455

CPC classification number: G01R31/2853 ,  G01R31/31717 ,  G06F17/5027 ,  Y10S370/916

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract translation: 公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。 本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。 逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板迹线。 还公开了一种用于硬件仿真系统的逻辑分析仪。 执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。