公开(公告)号：US20160379710A1

公开(公告)日：2016-12-29

申请号：US15039784

申请日：2014-12-04

Applicant: RAMBUS INC.

Inventor： Deepak Chandra SEKAR ,  Wayne Frederick ELLIS ,  Brent Steven HAUKNESS ,  Gary Bela BRONNER ,  Thomas VOGELSANG

IPC: G11C13/00

CPC classification number: G11C13/0028 ,  G11C7/08 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract translation: 存储器件包括多个电阻存储器单元和多个字线。 每个电阻性存储单元包括电阻性存储器元件，与电阻性存储元件串联电耦合的第一开关元件，以及与第一开关元件串联电耦合的第二开关元件。 每个电阻存储单元中的第一开关元件和第二开关元件耦合到不同的字线。

公开(公告)号：US20170004883A1

公开(公告)日：2017-01-05

申请号：US15100167

申请日：2014-12-03

Applicant: RAMBUS INC.

Inventor： Deepak Chandra SEKAR

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/003 ,  G11C13/0097 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

Abstract: A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a break for vias first on impedance or a second on impedance to the or dummies resistive memory element in response to a control signal.

Abstract translation: 存储器件包括分别耦合到多个存储器单元的本地位线和通过分别具有第一和第二阻抗的第一和第二可选择并行路径的全局位线。 第一路径在设置操作或形成操作中的至少一个中有效，并且第二路径在复位操作中有效。 用于选择存储器元件的选择器件包括具有第一掺杂级别的漏极和具有低于第一掺杂级别的第二掺杂级别的源，其中该器件被配置为首先提供阻抗上的通孔或第二阻抗 响应于控制信号到所述或虚拟电阻性存储元件。