公开(公告)号：US20160379710A1

公开(公告)日：2016-12-29

申请号：US15039784

申请日：2014-12-04

Applicant: RAMBUS INC.

Inventor： Deepak Chandra SEKAR ,  Wayne Frederick ELLIS ,  Brent Steven HAUKNESS ,  Gary Bela BRONNER ,  Thomas VOGELSANG

IPC: G11C13/00

CPC classification number: G11C13/0028 ,  G11C7/08 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract translation: 存储器件包括多个电阻存储器单元和多个字线。 每个电阻性存储单元包括电阻性存储器元件，与电阻性存储元件串联电耦合的第一开关元件，以及与第一开关元件串联电耦合的第二开关元件。 每个电阻存储单元中的第一开关元件和第二开关元件耦合到不同的字线。

公开(公告)号：US20240370331A1

公开(公告)日：2024-11-07

申请号：US18649009

申请日：2024-04-29

Applicant: Rambus Inc.

Inventor： Taeksang SONG ,  John Eric LINSTADT ,  Steven C. WOO ,  Craig E. HAMPEL ,  Brent Steven HAUKNESS ,  Christopher HAYWOOD

IPC: G06F11/10

Abstract: A random access memory device includes memory cells in each row for storing metadata related to accesses to that row. These metadata dedicated memory cells may store counter values that may be updated (e.g., incremented or decremented) when certain events occur (e.g., activate row—ACT, column read—CAS, error detected, etc.). Which events cause an update of the metadata stored in a row, and under what conditions related to the metadata/count value (e.g., threshold, match, threshold value, etc.) cause further action to be taken (e.g., alert controller, set mode register, etc.) are configurable by a controller. Additional functions related to the metadata/counters are also configurable such as scanning counter values to determine the row address with highest or lowest value and pattern matching (e.g., process identification match/mismatch).

公开(公告)号：US20240281154A1

公开(公告)日：2024-08-22

申请号：US18569518

申请日：2022-06-21

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Torsten PARTSCH ,  Brent Steven HAUKNESS ,  John Eric LINSTADT

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: DRAM cells need to be periodically refreshed to preserve the charge stored in them. The retention time is typically not the same for all DRAM cells but follows a distribution with multiple orders of magnitude difference between the retention time of cells with the highest charge loss and the cells with the lowest charge loss. Different refresh intervals are used for certain wordlines based on the required minimum retention time of the cells on those wordlines. The memory controller does not keep track of refresh addresses. After initialization of the DRAM devices, the memory controller issues a smaller number of refresh commands when compared to refreshing all wordlines at the same refresh interval.

公开(公告)号：US20170178723A1

公开(公告)日：2017-06-22

申请号：US15393233

申请日：2016-12-28

Applicant: RAMBUS INC.

Inventor： Brent Steven HAUKNESS

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0088 ,  G11C2213/79

Abstract: A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.