公开(公告)号：US12222871B2

公开(公告)日：2025-02-11

申请号：US18592424

申请日：2024-02-29

Applicant: Rambus Inc.

Inventor： Trung Diep ,  Hongzhong Zheng

IPC: G06F12/1009 ,  G06F12/0811 ,  G06F12/0864 ,  G11C7/10

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US12197354B2

公开(公告)日：2025-01-14

申请号：US18239689

申请日：2023-08-29

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/40 ,  G06F9/48 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4094 ,  H04L47/50

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US20210141737A1

公开(公告)日：2021-05-13

申请号：US16953230

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali

IPC: G06F12/1036 ,  G06F12/02

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

公开(公告)号：US10705988B2

公开(公告)日：2020-07-07

申请号：US16365528

申请日：2019-03-26

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/40 ,  G06F13/16 ,  H04L12/863 ,  G06F9/48 ,  G11C11/4076 ,  G11C11/4094

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US20190179768A1

公开(公告)日：2019-06-13

申请号：US16157908

申请日：2018-10-11

Applicant: Rambus Inc.

Inventor： Trung Diep ,  Hongzhong Zheng

IPC: G06F12/1009 ,  G11C7/10 ,  G06F12/0864 ,  G06F12/0811

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US20190121746A1

公开(公告)日：2019-04-25

申请号：US16134758

申请日：2018-09-18

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali

IPC: G06F12/1036 ,  G06F12/02

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

公开(公告)号：US09569393B2

公开(公告)日：2017-02-14

申请号：US13963391

申请日：2013-08-09

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/36 ,  G06F12/00 ,  G06F13/00 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F9/4881 ,  G06F13/1678 ,  G06F13/4059 ,  G06F2209/486 ,  G06F2209/5018 ,  G11C11/4076 ,  G11C11/4094

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract translation: 公开了一种通过具有主数据总线宽度的主数据总线在存储器控制器和至少一个存储器模块之间传送数据的方法。 该方法包括响应于来自存储器控制器的螺纹存储器请求经由对应的数据总线路径访问存储器件组中的第一个。 访问导致数据组共同形成通过对应的辅助数据总线路径传送的第一数据线程。 第一数据线程跨越主数据总线宽度的传输是在第一时间间隔内执行的，而在该第一时间间隔期间使用少于主数据传输连续吞吐量。 在第一时间间隔期间，在主数据总线上传送来自第二数据线程的至少一个数据组。

公开(公告)号：US08873329B1

公开(公告)日：2014-10-28

申请号：US13741308

申请日：2013-01-14

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent S. Haukness

IPC: G11C8/00 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C5/04 ,  G11C8/10 ,  G11C8/14

Abstract: Row activation operations within a memory component are carried out with respect to patterns of storage cells that constitute a fraction of a row and that have been predicted or predetermined to yield a succession of page hits, thus reducing activation power consumption without significantly increasing memory latency. The patterns of activated storage cells may be predicted or predetermined statically, for example, in response to user input or configuration settings that specify activation patterns to be applied in response to memory request traffic meeting various criteria, or dynamically through run-time evaluation of sequences of memory access requests.

Abstract translation: 存储器组件内的行激活操作相对于构成行的一小部分并且已被预测或预定以产生一连串页面命中的存储单元的模式来执行，从而在不显着增加存储器等待时间的情况下降低激活功率消耗。 激活的存储单元的模式可以静态地预测或预定，例如，响应于用户输入或配置设置，其指定响应于满足各种标准的存储器请求流量而应用的激活模式，或动态地通过序列的运行时评估 的内存访问请求。

公开(公告)号：US20140115296A1

公开(公告)日：2014-04-24

申请号：US14058081

申请日：2013-10-18

Applicant: Rambus Inc.

Inventor： Trung Diep ,  John Eric Linstadt ,  J. James Tringali ,  Hongzhong Zheng ,  Brent Steven Haukness

IPC: G06F12/10

CPC classification number: G06F12/0238 ,  G06F2212/7204 ,  G06F2212/7211 ,  G11C13/0028 ,  G11C13/0035 ,  G11C13/0069 ,  G11C29/50008 ,  G11C2029/0409 ,  G11C2213/72 ,  G11C2213/79

Abstract: A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group.

Abstract translation: 提出了一种操作包括存储器单元组的存储器件的方法。 这些组包括第一组记忆单元。 组中的每一个具有相应的物理地址，并且最初与相应的逻辑地址相关联。 该设备还包括具有物理地址但不是最初与逻辑地址相关联的附加组的存储器单元。 在该方法中，识别第一组存储器单元和附加的存储单元组之间的未来耐久性的差异。 当第一组和附加组之间的未来耐久性的差异超过预定阈值差时，第一组与最初与第一组相关联的逻辑地址之间的关联结束，并且附加组与逻辑地址相关联， 最初与第一组有关。

公开(公告)号：US20130097403A1

公开(公告)日：2013-04-18

申请号：US13652386

申请日：2012-10-15

Applicant: RAMBUS INC.

Inventor： Hongzhong Zheng ,  James Tringali

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0238 ,  G06F2212/7211 ,  Y02D10/13

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

Abstract translation: 存储器系统包括地址映射电路。 地址映射电路接收具有第一组地址位的输入存储器地址。 地址映射电路将逻辑功能应用于输入存储器地址以产生映射的存储器地址。 逻辑功能在分别确定映射的存储器地址的两个部分的两个单独的操作中使用第一组地址位的至少一个子集。