公开(公告)号：US20080091918A1

公开(公告)日：2008-04-17

申请号：US11952479

申请日：2007-12-07

申请人： Ravi Arimilli ,  Robert Cargnoni ,  Derek Williams ,  Kenneth Wright

发明人： Ravi Arimilli ,  Robert Cargnoni ,  Derek Williams ,  Kenneth Wright

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： H04L69/16 ,  G06F15/17 ,  H04L12/42 ,  H04L67/1002 ,  H04L69/161 ,  H04W28/14

摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

摘要翻译： 包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。 每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。 每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。

公开(公告)号：US20080109816A1

公开(公告)日：2008-05-08

申请号：US11971959

申请日：2008-01-10

申请人： RAVI ARIMILLI ,  Robert Cargnoni ,  Derek Williams ,  Kenneth Wright

发明人： RAVI ARIMILLI ,  Robert Cargnoni ,  Derek Williams ,  Kenneth Wright

IPC分类号： G06F9/50

CPC分类号： G06F9/30101

摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

摘要翻译： 包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。 每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率 无限流的加载，存储和无效命令。

公开(公告)号：US20050251622A1

公开(公告)日：2005-11-10

申请号：US10825188

申请日：2004-04-15

申请人： Ravi Arimilli ,  Robert Cargnoni ,  Hugh Shen ,  Derek Williams

发明人： Ravi Arimilli ,  Robert Cargnoni ,  Hugh Shen ,  Derek Williams

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0897 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3834 ,  G06F12/0804

摘要： A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.

摘要翻译： 一种方法和处理器系统，其基本上增强了存储队列条目的存储收集能力，以便能够在该条目被选择用于发送之前收集最大数量的接近时间存储操作。 为每个条目提供一个计数器，以跟踪从上次收集到条目的时间。 当计数器达到阈值饱和点之前没有发生新的聚合时，该信号将被发出准备就绪。 通过在计数器到期之前定义最佳阈值饱和点，为入口提供足够的时间来收集即时存储操作。 当某些条件发生时，条目可能被视为有资格进行选择，包括条目变满，发出屏障操作和计数器的饱和。 计数器的使用增加了存储队列条目完成收集足够的存储操作以在将该条目分派到RC机器之前更新整个高速缓存行的能力。

公开(公告)号：US20070226423A1

公开(公告)日：2007-09-27

申请号：US11388001

申请日：2006-03-23

申请人： Ravi Arimilli ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Ravi Arimilli ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0822 ,  G06F12/084

摘要： A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.

摘要翻译： 数据处理系统至少包括第一和第二相干域，每个域包括至少一个处理器核和存储器。 响应于指示要初始化的目标存储器块的处理器核心的初始化操作，第一相干域中的高速缓存存储器确定目标存储器块相对于高速缓冲存储器的一致性状态。 响应于该确定，高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。 响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围，并且响应于确定第一相关性域的第一相关性域和第二相关域 第二一致性状态。 然后，高速缓冲存储器播放具有所选范围的初始化请求。 响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。

公开(公告)号：US20060265553A1

公开(公告)日：2006-11-23

申请号：US11130907

申请日：2005-05-17

申请人： Ravi Arimilli ,  Derek Williams

发明人： Ravi Arimilli ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： In response to receiving an initialization operation from an associated processor core that indicates a target memory block to be initialized, a cache memory determines a coherency state of the target memory block. In response to a determination that the target memory block has a data-invalid coherency state with respect to the cache memory, the cache memory issues on a interconnect a corresponding initialization request indicating the target memory block. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value. The target memory block may thus be initialized without the cache memory holding a valid copy of the target memory block.

摘要翻译： 响应于从指示要初始化的目标存储器块的相关联的处理器核心接收到初始化操作，高速缓存存储器确定目标存储器块的一致性状态。 响应于目标存储器块相对于高速缓冲存储器具有数据无效一致性状态的确定，高速缓冲存储器在互连上发出指示目标存储器块的对应的初始化请求。 响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。 因此，可以初始化目标存储器块，而不使高速缓冲存储器保持目标存储器块的有效副本。

公开(公告)号：US20050251623A1

公开(公告)日：2005-11-10

申请号：US10825189

申请日：2004-04-15

申请人： Ravi Arimilli ,  Guy Guthrie ,  Hugh Shen ,  Derek Williams

发明人： Ravi Arimilli ,  Guy Guthrie ,  Hugh Shen ,  Derek Williams

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0804

摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.

摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。

公开(公告)号：US20070083716A1

公开(公告)日：2007-04-12

申请号：US11245312

申请日：2005-10-06

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Derek Williams ,  Kenneth Wright

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Derek Williams ,  Kenneth Wright

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.

摘要翻译： 一种用于在数据在第一耦合处理器的高速缓存中接收数据之前顺序耦合高速缓存行的连续处理器请求的方法。 同质和非均匀的操作彼此链接，并且一致性协议包括与链接状态相关联的几个新的中间一致性响应。 分配链接一致性状态以在第一处理器接收到数据之前跟踪处理器请求链和授予访问权限。 链接的一致性状态还标识接收处理器的地址。 当在链中的第一处理器的高速缓存处接收到数据时，处理器完成其对（或）数据的操作，然后将数据转发到链中的下一个处理器。 链接的一致性协议通过减少重试次数来释放地址总线带宽。

公开(公告)号：US20070083717A1

公开(公告)日：2007-04-12

申请号：US11245313

申请日：2005-10-06

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Derek Williams ,  Kenneth Wright

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Derek Williams ,  Kenneth Wright

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0822

摘要： A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of processor requests and subsequent access permission provided, prior to receipt of the data at the first processor starting the chain. The chained intermediate coherency state assigned identifies the processor operation and a directional identifier identifies the processor to which the cache line is to be forwarded. When the data is received at the cache of the first processor within the chain, the first processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chain is immediately stopped when a non-homogenous operation is snooped by the last-in-chain processor.

摘要翻译： 一种方法和数据处理系统，用于在数据在链中的第一处理器的高速缓存中接收之前，将链接中的高速缓存行的连续的均匀处理器请求顺序耦合。 分配链接的中间一致性状态，以便在启动链路的第一个处理器接收到数据之前跟踪处理器请求链和后续访问权限。 所分配的链接中间一致性状态标识处理器操作，并且方向标识符标识要向其转发高速缓存行的处理器。 当在链中的第一处理器的高速缓存处接收数据时，第一处理器完成其数据处理（或与数据）的操作，然后将数据转发到链中的下一个处理器。 当最后一个链接处理器窥探非均匀操作时，链条立即停止。

公开(公告)号：US08931908B2

公开(公告)日：2015-01-13

申请号：US12183647

申请日：2008-07-31

申请人： Derek Williams ,  Gary Garnier ,  Kent Stemer ,  Paul Carlson

发明人： Derek Williams ,  Gary Garnier ,  Kent Stemer ,  Paul Carlson

IPC分类号： B60R1/00 ,  F15D1/00

CPC分类号： F15D1/00 ,  G01N2021/151 ,  Y10T137/0324 ,  Y10T137/2082 ,  Y10T137/2224

摘要： An air purge apparatus and method is presented to protect an imaging system from contamination by particulate matter and other substances in the ambient environment. The apparatus is adapted to be placed adjacent to a viewing window, lens or optics of an imaging system and to provide a protective flow of air. The apparatus includes a curved surface to direct air from a first plenum toward an imaging path in front of the apparatus. The apparatus also includes one or more openings nearer the lens to direct air from a second plenum into the imaging path. The air from the first plenum entrains air from the second plenum and ambient air to create a fluid stream away from the viewing window, lens, or optics and may form a fluid barrier to reduce contamination of a volume of air in the imaging path of the imaging sensor.

摘要翻译： 提供了一种空气净化装置和方法，以保护成像系统免受周围环境中的颗粒物质和其他物质的污染。 该装置适于放置成与成像系统的观察窗，透镜或光学元件相邻并且提供保护性空气流。 该装置包括弯曲表面，用于将来自第一集气室的空气引向装置前面的成像路径。 该设备还包括靠近透镜的一个或多个开口以将空气从第二增压室引导到成像路径中。 来自第一增压室的空气带动来自第二增压室和环境空气的空气以产生远离观察窗，透镜或光学器件的流体流，并且可以形成流体屏障，以减少成像路径中的空气体积的污染 成像传感器。

公开(公告)号：US20080077377A1

公开(公告)日：2008-03-27

申请号：US11948461

申请日：2007-11-30

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Within a display device, a respective one of a plurality of design graphical representations is displayed for each of a plurality of hierarchically arranged design entity instances within a simulated system. The design entity instances include a particular design entity instance containing a latch that is represented by a particular design graphical representation. A configuration entity instance associated with the particular design entity is identified within a configuration database associated with the simulated system. The configuration entity instance has a plurality of different settings that each reflects a value of the latch. Within the display device, a configuration graphical representation of the configuration entity instance is presented in association with the particular design graphical representation corresponding to the particular design entity instance. In addition, a current setting of the configuration entity instance is presented concurrently with the configuration graphical representation.