公开(公告)号：US20050251622A1

公开(公告)日：2005-11-10

申请号：US10825188

申请日：2004-04-15

申请人： Ravi Arimilli ,  Robert Cargnoni ,  Hugh Shen ,  Derek Williams

发明人： Ravi Arimilli ,  Robert Cargnoni ,  Hugh Shen ,  Derek Williams

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0897 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3834 ,  G06F12/0804

摘要： A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.

摘要翻译： 一种方法和处理器系统，其基本上增强了存储队列条目的存储收集能力，以便能够在该条目被选择用于发送之前收集最大数量的接近时间存储操作。 为每个条目提供一个计数器，以跟踪从上次收集到条目的时间。 当计数器达到阈值饱和点之前没有发生新的聚合时，该信号将被发出准备就绪。 通过在计数器到期之前定义最佳阈值饱和点，为入口提供足够的时间来收集即时存储操作。 当某些条件发生时，条目可能被视为有资格进行选择，包括条目变满，发出屏障操作和计数器的饱和。 计数器的使用增加了存储队列条目完成收集足够的存储操作以在将该条目分派到RC机器之前更新整个高速缓存行的能力。

公开(公告)号：US20070250669A1

公开(公告)日：2007-10-25

申请号：US11380020

申请日：2006-04-25

申请人： Ravi Arimilli ,  Thomas Capasso ,  Robert Cargnoni ,  Guy Guthrie ,  Hugh Shen ,  William Starke

发明人： Ravi Arimilli ,  Thomas Capasso ,  Robert Cargnoni ,  Guy Guthrie ,  Hugh Shen ,  William Starke

IPC分类号： G06F13/00

CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/544

摘要： A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.

摘要翻译： 数据处理系统包括处理器核心和存储器子系统。 存储器子系统包括具有多个条目的存储队列，其中每个条目包括用于保存存储操作的目标地址的地址字段，用于保存用于存储操作的数据的数据字段和指示存在或不存在的虚拟同步字段 与该条目相关联的同步操作。 存储器子系统还包括存储队列控制器，其响应于在存储器子系统处的接收包括同步操作和特定存储操作的一系列操作，将特定存储操作的目标地址和数据放置在地址字段和数据中 字段，并且设置条目的虚拟同步字段以表示同步操作，使得减少使用的存储队列条目的数量。

公开(公告)号：US20050251623A1

公开(公告)日：2005-11-10

申请号：US10825189

申请日：2004-04-15

申请人： Ravi Arimilli ,  Guy Guthrie ,  Hugh Shen ,  Derek Williams

发明人： Ravi Arimilli ,  Guy Guthrie ,  Hugh Shen ,  Derek Williams

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0804

摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.

摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。

公开(公告)号：US20070250668A1

公开(公告)日：2007-10-25

申请号：US11380018

申请日：2006-04-25

申请人： Ravi Arimilli ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  William Starke

发明人： Ravi Arimilli ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  William Starke

IPC分类号： G06F13/00

CPC分类号： G06F13/1631 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0846 ,  G06F12/0888

摘要： A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing system further includes a mode field having a first setting indicating strong ordering between store operations and a second setting indicating weak ordering between store operations. Store operations accessing the memory subsystem are associated with either the first setting or the second setting. The data processing system also includes logic that, based upon settings of the mode field, inserts a synchronizing operation between a store operation associated with the first setting and a store operation associated with the second setting, such that all store operations preceding the synchronizing operation complete before store operations subsequent to the synchronizing operation.

摘要翻译： 数据处理系统包括存储器子系统和执行单元，其耦合到存储器子系统，其执行存储指令以确定要由存储器子系统执行的存储操作的目标存储器地址。 数据处理系统还包括具有指示存储操作之间的强顺序的第一设置的模式字段和指示存储操作之间的弱顺序的第二设置。 访问内存子系统的存储操作与第一个设置或第二个设置相关联。 数据处理系统还包括基于模式字段的设置的逻辑，在与第一设置相关联的存储操作与与第二设置相关联的存储操作之间插入同步操作，使得同步操作之前的所有存储操作完成 在同步操作之后的存储操作之前。

公开(公告)号：US20060184746A1

公开(公告)日：2006-08-17

申请号：US11056679

申请日：2005-02-11

申请人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F13/1605 ,  G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 监听请求被输入到停止/重新排序单元的第一可用锁存器中，除非停止/重新排序单元已满，在这种情况下，新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。 侦听请求具有比来自处理器的请求更高的优先级，并且仲裁机制通过处理器请求选择侦听请求，除非仲裁机制另请求（“停止请求”）到停止/重新排序单元。 通过具有比处理器请求更高优先级的侦听请求，减少了被拒绝的侦听请求的数量。 通过使仲裁机制发出停顿请求，处理器不会饿死。

公开(公告)号：US20070277026A1

公开(公告)日：2007-11-29

申请号：US11836872

申请日：2007-08-10

申请人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

发明人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F9/00

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F12/0897

摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

公开(公告)号：US20060184749A1

公开(公告)日：2006-08-17

申请号：US11056764

申请日：2005-02-11

申请人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.

公开(公告)号：US20060090035A1

公开(公告)日：2006-04-27

申请号：US10970437

申请日：2004-10-21

申请人： Guy Guthrie ,  Hugh Shen ,  Derek Williams

发明人： Guy Guthrie ,  Hugh Shen ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3851

摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.

公开(公告)号：US20080086605A1

公开(公告)日：2008-04-10

申请号：US11952596

申请日：2007-12-07

申请人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

发明人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F12/16

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F12/0897

摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

公开(公告)号：US20060179226A1

公开(公告)日：2006-08-10

申请号：US11054450

申请日：2005-02-09

申请人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/3824 ,  G06F12/0817

摘要： A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.

摘要翻译： 一种用于重新排序从处理器核到存储队列的存储操作的系统和方法。 当存储队列从处理器核心接收到新的处理器发出的存储操作时，存储队列控制器在存储队列中分配新的条目。 响应于在商店队列中分配新条目，商店队列控制器确定新条目是否依赖于商店队列中的至少一个其他有效条目。 响应于确定新条目取决于存储队列中的至少一个其他有效条目，存储队列控制器禁止向RC调度逻辑请求新条目，直到新条目依赖于其上的每个有效条目已经成功 通过RC调度逻辑调度到RC机器。