公开(公告)号：US20250030428A1

公开(公告)日：2025-01-23

申请号：US18223365

申请日：2023-07-18

Applicant: RAYTHEON COMPANY

Inventor： Magathi Willis ,  Micky R. Harris

IPC: H03L7/099 ,  H03L7/085

Abstract: A system for automatically calibrating a phase locked loop (PLL), the system comprising: a node a voltage controlled oscillator (VCO) coupled to the node and configured to provide an output signal to the node; at least one digital-to-analog converter (DAC) coupled to the VCO and configured to provide a voltage to the VCO; and at least one controller configured to: determine an output frequency of the output signal; responsive to determining the output frequency, compare the output frequency to the voltage; responsive to determining the output frequency, compare the output frequency to a target frequency; and control the DAC to modify the voltage based on a comparison of the output frequency to the voltage and a comparison of the output frequency to the target frequency.

公开(公告)号：US20250030421A1

公开(公告)日：2025-01-23

申请号：US18223371

申请日：2023-07-18

Applicant: RAYTHEON COMPANY

Inventor： Magathi Willis ,  Micky R. Harris

IPC: H03K19/00 ,  H03K17/06 ,  H03K17/693 ,  H03K19/173

Abstract: A configurable driver is presented, comprising: a first transistor of a first type coupled to a first node; a second transistor of the first type coupled to a second node; a first transistor of a second type coupled to the first node; a second transistor of a second type coupled to the second node; a first multiplexer coupled to a gate of the first transistor of the first type; a second multiplexer coupled to a gate of the second transistor of the first type; a third multiplexer coupled to a gate of the first transistor of the second type; a fourth multiplexer coupled to a gate of the second transistor of the second type; and one or more switching devices coupled between the first node and the second node.