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公开(公告)号：US20150318622A1
公开(公告)日：2015-11-05
申请号：US14267685
申请日：2014-05-01
Applicant: RAYTHEON COMPANY
Inventor： James A. Pruett , Thomas T. Leise , Jerry M. Grimm
CPC classification number: H01Q5/42 , H01Q21/0006 , H01Q21/061 , H01Q21/24 , H01Q21/30
Abstract: An array antenna including two interleaved array antennas, capable of being operated independently at a first frequency, or together, at a second frequency. Each of the two array antennas is composed of alternating elements of an antenna array, and the two arrays are interleaved. Each of the interleaved arrays may be operated independently, e.g., in the X band, or the arrays may be driven together, as a single array with more densely spaced elements, e.g., in the Ku band.
Abstract translation: 一种包括两个交错阵列天线的阵列天线，能够以第一频率或第二频率一起独立地操作。 两个阵列天线中的每一个由天线阵列的交替元件组成，并且两个阵列被交织。 每个交错阵列可以独立地操作，例如在X频带中，或者阵列可以一起驱动，作为具有更密集间隔的元件的单个阵列，例如在Ku波段中。
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Patent Agency Ranking
公开(公告)号：US11837524B2
公开(公告)日：2023-12-05
申请号：US17352612
申请日：2021-06-21
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Kalin Spariosu , Thomas T. Leise , David A. Vasquez , Michael R. Patrizi
Abstract: A cooling device for integrated circuits. The device includes: a plurality TEC cooling cells arranged in an array, wherein each of the cells includes a controller coupled to at least one TEC device; and a single power connector that provides power to all the cells in the array. The controller of each cell in the array is operable to control the at least one TEC it is coupled to with power received from the single power connector.
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公开(公告)号：US20220406680A1
公开(公告)日：2022-12-22
申请号：US17352612
申请日：2021-06-21
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Kalin Spariosu , Thomas T. Leise , David A. Vasquez , Michael R. Patrizi
Abstract: A cooling device for integrated circuits. The device includes: a plurality TEC cooling cells arranged in an array, wherein each of the cells includes a controller coupled to at least one TEC device; and a single power connector that provides power to all the cells in the array. The controller of each cell in the array is operable to control the at least one TEC it is coupled to with power received from the single power connector.
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公开(公告)号：US12107945B2
公开(公告)日：2024-10-01
申请号：US18154117
申请日：2023-01-13
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Ro S. Ko , Thomas T. Leise , Edward Escandon
IPC: H04L7/00
CPC classification number: H04L7/0008
Abstract: An electrical signal delay calibration system includes a device under test (DUT) and a digital signal processing chip including a plurality of signal lanes. Each signal lane includes a receive signal path in signal communication with a respective DUT receive path and a transmit signal path in signal communication with a respective DUT transmit path. A processor is configured to determine transmit pulse timestamps assigned to transmit signals transmitted on the transmit signal paths and to determine receive pulse timestamps assigned to receive signals received from the receive signal paths. The processor determines a lane asymmetry associated with each signal lane based on at least one of the transmit pulse timestamps and at least one of the receive pulse timestamps, and removes each of the lane asymmetries to minimize a signal delay in each signal lane among the plurality of signal lanes.
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公开(公告)号：US20240243897A1
公开(公告)日：2024-07-18
申请号：US18154117
申请日：2023-01-13
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Ro S. Ko , Thomas T. Leise , Edward Escandon
IPC: H04L7/00
CPC classification number: H04L7/0008
Abstract: An electrical signal delay calibration system includes a device under test (DUT) and a digital signal processing chip including a plurality of signal lanes. Each signal lane includes a receive signal path in signal communication with a respective DUT receive path and a transmit signal path in signal communication with a respective DUT transmit path. A processor is configured to determine transmit pulse timestamps assigned to transmit signals transmitted on the transmit signal paths and to determine receive pulse timestamps assigned to receive signals received from the receive signal paths. The processor determines a lane asymmetry associated with each signal lane based on at least one of the transmit pulse timestamps and at least one of the receive pulse timestamps, and removes each of the lane asymmetries to minimize a signal delay in each signal lane among the plurality of signal lanes.
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公开(公告)号：US09843098B2
公开(公告)日：2017-12-12
申请号：US14267685
申请日：2014-05-01
Applicant: RAYTHEON COMPANY
Inventor： James A. Pruett , Thomas T. Leise , Jerry M. Grimm
CPC classification number: H01Q5/42 , H01Q21/0006 , H01Q21/061 , H01Q21/24 , H01Q21/30
Abstract: An array antenna including two interleaved array antennas, capable of being operated independently at a first frequency, or together, at a second frequency. Each of the two array antennas is composed of alternating elements of an antenna array, and the two arrays are interleaved. Each of the interleaved arrays may be operated independently, e.g., in the X band, or the arrays may be driven together, as a single array with more densely spaced elements, e.g., in the Ku band.
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