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公开(公告)号：US20220231892A1
公开(公告)日：2022-07-21
申请号：US17571560
申请日：2022-01-10
发明人： YI-TING LIU , JIAN LIU
摘要： A receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes: a signal receiving terminal for receiving the input signal; a link equalizer circuit (LEQ) having a first input terminal coupled to the signal receiving terminal; and an out-of-band signaling (OOBS) circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; and a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal receives a voltage, and the output terminal is coupled to the LEQ or the OOBS circuit. The first input terminal of the LEQ and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.
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公开(公告)号：US20200021425A1
公开(公告)日：2020-01-16
申请号：US16507504
申请日：2019-07-10
发明人： JIAN LIU , WEIXIONG HE , JIANING LOU
摘要： Disclosed is a clock generating circuit including a filter and a ring oscillator. The filter receives an input signal and accordingly determines a first voltage signal and a second voltage signal that are outputted via a first node and a second node respectively. The filter includes a first filtering circuit and a second filtering circuit coupled in parallel between the first node and a reference voltage terminal; the second filtering circuit includes a switch and a capacitor connected in series, in which the second node is between the switch and the capacitor, and the switch is turned off in an analog clock data recovery (ACDR) mode and turned on in a clock multiplication unit (CMU) mode. The ring oscillator outputs at least one clock according to the first voltage signal in the ACDR mode and outputs at least one clock according to the second voltage signal in the CMU mode.
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公开(公告)号：US20190334693A1
公开(公告)日：2019-10-31
申请号：US16394106
申请日：2019-04-25
发明人： JIAN LIU , CHI-KUNG KUAN
摘要： Disclosed is a clock data recovery (CDR) device including a master lane circuit and a plurality of slave lane circuits. The master lane circuit includes: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO), and a loop divider; a master lane sampling circuit; a master lane phase detector (PD); and a master lane multiplexer coupled between the master lane PD and the CP and between the PFD and the CP. Each slave lane circuit includes: a slave lane sampling circuit (SLS); a slave lane PD; a slave lane digital loop filter; a phase rotator (PR); and a slave lane multiplexer coupled between the VCO and the SLS and between the PR and the SLS, in which the master lane multiplexer and the slave lane multiplexers are configured to have the CDR device operate in one of multiple modes.
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公开(公告)号：US20220029629A1
公开(公告)日：2022-01-27
申请号：US17228764
申请日：2021-04-13
发明人： JUN YANG , JIA-NING LOU , ZHI-XIAN GAO , JIAN LIU
摘要： A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.
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公开(公告)号：US20190386682A1
公开(公告)日：2019-12-19
申请号：US16437446
申请日：2019-06-11
发明人： JIAN LIU , CHI-KUNG KUAN
摘要： Disclosed is a Serializer/Deserializer physical layer circuit (SerDes PHY) for receiving and transmitting data in a half-duplex manner, the SerDes PHY including: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a low pass filter, a voltage-controlled oscillator (VCO) and a loop divider; a sampling circuit sampling a received signal according to clocks from the VCO in a receive mode; a phase detector (PD) operating according to outputs of the sampling circuit; a multiplexer connecting the PD with the CP and disconnecting the PFD from the CP in the receive mode, and connecting the PFD with the CP and disconnecting the PD from the CP in a transmission mode; a parallel-to-serial converter converting parallel data into serial data according a clock from the VCO in the transmission mode; and a transmission driver outputting a transmission signal according to the serial data in the transmission mode.
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