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1.发明申请公开(公告)号：US20230116785A1
公开(公告)日：2023-04-13
申请号：US17870958
申请日：2022-07-22
发明人： JUN YANG , SHIH-HSIUNG HUANG , YEN-TING WU
摘要： A successive approximation register analog to digital converter device includes first and second digital to analog converter (DAC) circuits, a comparator circuit, a controller circuit, and a dynamic element matching (DEM) circuit. The first and second DAC circuits samples an input signal. The comparator circuit and the controller circuit generate first and second bits according to outputs of the first and second DAC circuits. The DEM circuit encodes the first bits to generate third bits, in order to refresh the first DAC circuit. After the first DAC circuit is refreshed, the controller circuit resets partial bits in the second bits. After the partial bits are reset, the comparator circuit generates comparison results according to outputs of the first and second DAC circuits. The controller circuit generates fourth bits according to the comparison results, and generates a digital output according to the first, second, and fourth bits.
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公开(公告)号：US20220029629A1
公开(公告)日：2022-01-27
申请号：US17228764
申请日：2021-04-13
发明人： JUN YANG , JIA-NING LOU , ZHI-XIAN GAO , JIAN LIU
摘要： A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.
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公开(公告)号：US20210099132A1
公开(公告)日：2021-04-01
申请号：US16868853
申请日：2020-05-07
发明人： HENG-CHIA HSU , JUN YANG
摘要： An amplifier device includes an alternate current (AC) coupling circuit, an amplifier circuit, and a first bias circuit. The amplifier circuit is configured to amplify an input signal to generate an output signal, in which the amplifier circuit includes a first input terminal, and the first input terminal receives the input signal via the AC coupling circuit. The first bias circuit is configured to apply a first bias voltage to the first input terminal according to one of the output signal and a first voltage, such that the amplifier circuit amplifies the input signal to output the output signal.
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公开(公告)号：US20220337158A1
公开(公告)日：2022-10-20
申请号：US17562388
申请日：2021-12-27
发明人： JUN YANG
摘要： The present invention discloses a voltage conversion circuit having self-adaptive mechanism. A control branch includes a first resistor coupled between a second power supply and a control terminal, and a switch circuit that is coupled between the control terminal and a ground terminal and receives an input voltage from an input terminal to generate a control voltage at the control terminal. A voltage-withstanding P-type transistor circuit of an output branch is coupled between the second power supply and the output terminal that generates an output voltage and is controlled by the control voltage. A voltage-withstanding N-type transistor circuit of the output branch is coupled between the output terminal and the ground terminal and is controlled by an inverted input voltage. When the input voltage is at a first power domain high/low state, the output voltage is at a second power domain high/low state.
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公开(公告)号：US20220077774A1
公开(公告)日：2022-03-10
申请号：US17326396
申请日：2021-05-21
发明人： JUN YANG , JIA-NING LOU
摘要： A charge pump device includes first to third current source circuits, a first switch, and a second switch. The first current source circuit is implemented with a first type transistor, and provides a first current to an output node. The first switch is selectively turned on according to a first control signal. When the first switch is turned on, the second current source circuit drains a second current from the output node. The second switch is selectively turned on according to a second control signal. Each of the first switch and the second switch is implemented with a second type transistor, and a withstand voltage of the first type transistor is higher than a withstand voltage of the second type transistor. When the second switch is turned on, the third current source circuit drains a third current from the output node.
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公开(公告)号：US20230163770A1
公开(公告)日：2023-05-25
申请号：US17946521
申请日：2022-09-16
发明人： SHIH-HSIUNG HUANG , JUN YANG , YU-CHANG CHEN
IPC分类号： H03M1/06
CPC分类号： H03M1/0604
摘要： A time-interleaved analog-to-digital converter (TIADC) operates in a first mode or a second mode and includes M analog-to-digital converters (ADCs), a reference ADC, a digital correction circuit, and a control circuit. The M ADCs sample an input signal according to M enable signals to generate M digital output codes. The reference ADC samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock. The control circuit outputs the M corrected digital output codes in turn but does not output the reference digital output code in the first mode and randomly outputs the M corrected digital output codes and the reference digital output code in the second mode.
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公开(公告)号：US20230098370A1
公开(公告)日：2023-03-30
申请号：US17739065
申请日：2022-05-06
发明人： JUN YANG
摘要： A driving current includes a first and second push-pull circuits which each includes a first and second output terminals and a first to fourth transistors. The first to fourth transistors are series connected. At least one of control terminals of the first and second transistors of the first push-pull circuit and at least one of control terminals of the third and fourth transistors of the second push-pull circuit receive a positive input signal. At least one of control terminals of the third and fourth transistors of the first push-pull circuit and at least one of control terminals of the first and second transistors of the second push-pull circuit receive a negative input signal. The first output terminals output a pair of first signals. The second output terminals output a pair of second signals.
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