公开(公告)号：US20190163655A1

公开(公告)日：2019-05-30

申请号：US16151161

申请日：2018-10-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kyohei YAMAGUCHI ,  Daisuke KAWAKAMI ,  Hiroyuki HAMASAKI

IPC: G06F13/24

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

公开(公告)号：US20160349322A1

公开(公告)日：2016-12-01

申请号：US15093988

申请日：2016-04-08

Applicant: Renesas Electronics Corporation

Inventor： Shinichi SHIBAHARA ,  Daisuke KAWAKAMI ,  Yutaka IGAKU

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G06F11/27

Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.

Abstract translation: 一种半导体装置，包括存储电路，处理电路，其使用存储在存储电路中的数据进行处理，并且在执行处理时将数据写入存储电路;扫描测试电路，当处理电路执行对处理电路的扫描测试时 电路不执行处理，以及抑制电路，当执行对处理电路的扫描测试时，禁止将数据从处理电路写入存储电路。

公开(公告)号：US20230146281A1

公开(公告)日：2023-05-11

申请号：US17951294

申请日：2022-09-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuo AITA ,  Daisuke KAWAKAMI ,  Toshiyuki HIRAKI

IPC: G11C29/54 ,  G06F12/109

CPC classification number: G11C29/54 ,  G06F12/109 ,  G06F2212/657

Abstract: A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.

公开(公告)号：US20210263869A1

公开(公告)日：2021-08-26

申请号：US17319799

申请日：2021-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kyohei YAMAGUCHI ,  Daisuke KAWAKAMI ,  Hiroyuki HAMASAKI

IPC: G06F13/24 ,  G06F11/07

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

公开(公告)号：US20190072611A1

公开(公告)日：2019-03-07

申请号：US16180111

申请日：2018-11-05

Applicant: Renesas Electronics Corporation

Inventor： Shinichi SHIBAHARA ,  Daisuke KAWAKAMI ,  Yutaka IGAKU

IPC: G01R31/3177 ,  G06F11/27 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G06F11/27

Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.