公开(公告)号：US20190163655A1

公开(公告)日：2019-05-30

申请号：US16151161

申请日：2018-10-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kyohei YAMAGUCHI ,  Daisuke KAWAKAMI ,  Hiroyuki HAMASAKI

IPC: G06F13/24

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

公开(公告)号：US20240143465A1

公开(公告)日：2024-05-02

申请号：US18452305

申请日：2023-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyoshi HAYASE ,  Yuki HAYAKAWA ,  Toshiyuki KAYA ,  Kyohei YAMAGUCHI ,  Takahiro IRITA ,  Shinichi SHIBAHARA

IPC: G06F11/22

CPC classification number: G06F11/2284

Abstract: A semiconductor device includes first and second processor cores configured to perform a lock step operation and including first and second scan chains. The semiconductor device further includes a scan test control unit that controls a scan test of the first and second processor cores using the first and second scan chains, and a start-up control unit that outputs a reset signal for bringing the first and second processor cores into a reset state. The start-up control unit outputs an initialization scan request before the start of a lock step operation, and the scan test control unit performs an initialization scan test operation on the first and second processor cores by using an initialization pattern.

公开(公告)号：US20210263869A1

公开(公告)日：2021-08-26

申请号：US17319799

申请日：2021-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kyohei YAMAGUCHI ,  Daisuke KAWAKAMI ,  Hiroyuki HAMASAKI

IPC: G06F13/24 ,  G06F11/07

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.