公开(公告)号：US20150236156A1

公开(公告)日：2015-08-20

申请号：US14700461

申请日：2015-04-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Hidetatsu NAKAMURA ,  Akihito SAKAKIDANI ,  Eiichirou WATANABE

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L29/7843 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66636

Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.

Abstract translation: 半导体器件包括MISFET。 半导体器件还包括氮化硅膜12和布置在氮化硅膜12上的氮化硅膜10.氮化硅膜12覆盖MISFET的源极/漏极8的上部的至少一部分，并且具有 膜厚度比栅电极4的高度薄。源极/漏极8在其与氮化硅膜10的边界上包括硅化镍9。氮化硅膜10是应力膜。 氮化硅膜12与源极/漏极8的表面之间以及氮化硅膜12和氮化硅膜10之间的紧密附着性比使用氮化硅膜10 使其牢固地粘附到源/漏8。