公开(公告)号：US20170373145A1

公开(公告)日：2017-12-28

申请号：US15631257

申请日：2017-06-23

Applicant: Renesas Electronics Corporation

Inventor： Hiroki SHINKAWATA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: In an SOI substrate having a semiconductor substrate serving as a support substrate, an insulating layer on the semiconductor substrate and a semiconductor layer on the insulating layer, an element isolation region which penetrates the semiconductor layer and the insulating layer and whose bottom part reaches the semiconductor substrate is formed, and a gate electrode is formed on the semiconductor layer via a gate insulating film. A divot is formed in the element isolation region at a position adjacent to the semiconductor layer, and a buried insulating film is formed in the divot. The gate electrode includes a part formed on the semiconductor layer via the gate insulating film, a part located on the buried insulating film and a part located on the element isolation region.

公开(公告)号：US20220068706A1

公开(公告)日：2022-03-03

申请号：US17369714

申请日：2021-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MAEDA ,  Tatsuyoshi MIHARA ,  Hiroki SHINKAWATA

IPC: H01L21/762 ,  H01L27/11 ,  H01L27/12 ,  H01L21/304

Abstract: Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.

公开(公告)号：US20160293507A1

公开(公告)日：2016-10-06

申请号：US15060360

申请日：2016-03-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki SHINKAWATA

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.

Abstract translation: 半导体器件减少测量时间。 根据本发明实施例的半导体器件包括：用于测试的多个串联电阻元件; 耦合到耦合所述电阻元件的耦合路径的多个开关; 以及多个选择电路，通过接通或断开开关来选择待测量的串联电阻元件的数量。 在半导体器件中：开关包括耦合到多组电阻元件的多个第一开关，每个组包括电阻元件的N（N = 2或更大整数）; 并且选择电路接通或关闭第一开关，从而选择要测量的多个串联电阻元件作为一组，该数量等于N.

公开(公告)号：US20150287746A1

公开(公告)日：2015-10-08

申请号：US14674838

申请日：2015-03-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki SHINKAWATA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L21/027 ,  H01L29/167 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0207 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78621

Abstract: In a step F2, an isolation region and an element formation region are formed in an SOI substrate. In a step F3, an SOI region and a bulk region are formed. Here, an isolation insulating film of the isolation region is exposed along the entire perimeter of a sidewall of a step between the SOI region and the bulk region. In a step F4, a gate electrode is formed. In a step F5, extension implantation of a bulk transistor is carried out. Here, treatment for preventing an impurity for extension implantation from being implanted into the SOI region is performed. In a step F6, an elevated epitaxial layer is formed in the SOI region.

Abstract translation: 在步骤F2中，在SOI衬底中形成隔离区域和元件形成区域。 在步骤F3中，形成SOI区域和体区域。 这里，隔离区域的隔离绝缘膜沿着SOI区域和主体区域之间的台阶侧壁的整个周边露出。 在步骤F4中，形成栅电极。 在步骤F5中，进行体晶体管的延伸注入。 这里，进行用于防止用于延伸注入的杂质的注入到SOI区域的处理。 在步骤F6中，在SOI区域中形成升高的外延层。

公开(公告)号：US20180040523A1

公开(公告)日：2018-02-08

申请号：US15788490

申请日：2017-10-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki SHINKAWATA

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.