公开(公告)号：US20240136419A1

公开(公告)日：2024-04-25

申请号：US17969904

申请日：2022-10-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MAEDA ,  Yoshiyuki KAWASHIMA

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/788 ,  H01L29/792

Abstract: A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.

公开(公告)号：US20240234528A9

公开(公告)日：2024-07-11

申请号：US17969904

申请日：2022-10-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MAEDA ,  Yoshiyuki KAWASHIMA

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/788 ,  H01L29/792

Abstract: A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.

公开(公告)号：US20220068706A1

公开(公告)日：2022-03-03

申请号：US17369714

申请日：2021-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MAEDA ,  Tatsuyoshi MIHARA ,  Hiroki SHINKAWATA

IPC: H01L21/762 ,  H01L27/11 ,  H01L27/12 ,  H01L21/304

Abstract: Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.