公开(公告)号：US20240274670A1

公开(公告)日：2024-08-15

申请号：US18642509

申请日：2024-04-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20200013857A1

公开(公告)日：2020-01-09

申请号：US16575836

申请日：2019-09-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20170301694A1

公开(公告)日：2017-10-19

申请号：US15634439

申请日：2017-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/324 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/66537 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78684

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

公开(公告)号：US20160181147A1

公开(公告)日：2016-06-23

申请号：US15054696

申请日：2016-02-26

Applicant: Renesas Electronics Corporation

Inventor： Jiro YUGAMI ,  Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA ,  Yasuo INOUE ,  Yoshiki YAMAMOTO

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

公开(公告)号：US20160155825A1

公开(公告)日：2016-06-02

申请号：US15017459

申请日：2016-02-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiaki IWAMATSU ,  Takashi TERADA ,  Hirofumi SHINOHARA ,  Kozo ISHIKAWA ,  Ryuta TSUCHIYA ,  Kiyoshi HAYASHI

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/308 ,  H01L21/321

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

公开(公告)号：US20140375379A1

公开(公告)日：2014-12-25

申请号：US14310731

申请日：2014-06-20

Applicant: Renesas Electronics Corporation

Inventor： Hideki MAKIYAMA ,  Toshiaki IWAMATSU

IPC: G05F1/625

CPC classification number: H03K17/687 ,  G05F1/625 ,  H01L27/1203 ,  H01L29/78 ,  H03K2217/0018

Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.

Abstract translation: 作为电流监视电路，半导体集成电路器件具有其中n沟道型MISFET彼此串联连接的电路。 基于将衬底偏压施加到p沟道型MISFET的状态下的速度监视器电路的延迟时间，确定要施加到p沟道型MISFET的第一衬底偏置的第一电压值。 接下来，基于在第一衬底偏压被施加到电流监视电路的p沟道型MISFET的状态下流过n沟道型MISFET的电流，并且第二衬底偏置被施加到n沟道 确定要施加到n沟道型MISFET的第二衬底偏置的第二电压值。

公开(公告)号：US20200343268A1

公开(公告)日：2020-10-29

申请号：US16928542

申请日：2020-07-14

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20160005765A1

公开(公告)日：2016-01-07

申请号：US14855150

申请日：2015-09-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi SHINOHARA ,  Hidekazu ODA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L27/1203 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66598 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835

Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

公开(公告)号：US20150221668A1

公开(公告)日：2015-08-06

申请号：US14615336

申请日：2015-02-05

Applicant: Renesas Electronics Corporation

Inventor： Katsuyuki HORITA ,  Toshiaki IWAMATSU ,  Hideki MAKIYAMA

IPC: H01L27/12 ,  H01L27/11 ,  H01L27/092

CPC classification number: H01L27/1203 ,  G11C11/412 ,  H01L21/2652 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/78648

Abstract: A semiconductor device with an SRAM memory cell having improved characteristics.Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

Abstract translation: 具有SRAM存储单元的具有改进特性的半导体器件。 在其中放置包括SRAM的驱动器晶体管的有源区域之下，经由绝缘层提供被元件隔离区域包围的n型背栅极区域。 它耦合到驱动晶体管的栅极电极。 p型阱区域设置在n型背栅区域的下方，并且至少部分延伸到比元件隔离区域更深的位置。 它固定在接地电位。 这样的结构使得可以在晶体管导通时控制晶体管的阈值电位为高，并且当晶体管截止时，晶体管的阈值电位变低; 并且控制以便不对p阱区域和n型背栅极区域之间的PN结施加正向偏压。

公开(公告)号：US20130119469A1

公开(公告)日：2013-05-16

申请号：US13675682

申请日：2012-11-13

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1207 ,  H01L29/78648

Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.