公开(公告)号：US11444010B2

公开(公告)日：2022-09-13

申请号：US17060545

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazunori Hasegawa ,  Yuichi Yato ,  Hiroyuki Nakamura ,  Yukihiro Sato ,  Hiroya Shimoyama

IPC: H01L23/495 ,  H01L23/48 ,  H01L21/00 ,  H05K7/02 ,  H05K7/18 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.

公开(公告)号：US10468338B2

公开(公告)日：2019-11-05

申请号：US16048284

申请日：2018-07-29

Applicant: Renesas Electronics Corporation

Inventor： Hiroya Shimoyama ,  Hiroyuki Nakamura

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H05K7/20 ,  H01L25/07 ,  H01L23/36 ,  H02M7/537

Abstract: Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and third semiconductor chips each incorporating a power transistor for high-side switch, fourth, fifth, and sixth semiconductor chips each incorporating a power transistor for low-side switch, and a semiconductor chip incorporating a control circuit controlling these chips. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD9 and a plurality of leads LD10 via a metal plate. As viewed in a plane, the leads LD9 intersect with a side MRd4 of the sealing portion and the leads LD10 intersect with a side MRd2 of the sealing portion.

公开(公告)号：US10204849B2

公开(公告)日：2019-02-12

申请号：US15850009

申请日：2017-12-21

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki Nakamura ,  Hiroya Shimoyama

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/04 ,  H01L31/111 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L27/06 ,  H01L29/66 ,  H02M7/00 ,  H02M7/537 ,  H02P27/06 ,  B62D5/04

Abstract: The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.