公开(公告)号：US20130249624A1

公开(公告)日：2013-09-26

申请号：US13900210

申请日：2013-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Mihoko AKIYAMA ,  Futoshi IGAUE ,  Kenji YOSHINAGA ,  Masashi MATSUMURA ,  Fukashi MORISHITA

IPC: G05F1/46

CPC classification number: G05F1/468 ,  G11C5/025 ,  G11C5/147

Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。