公开(公告)号：US20150228341A1

公开(公告)日：2015-08-13

申请号：US14691125

申请日：2015-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoya WATANABE ,  Isamu HAYASHI ,  Teruhiko AMANO ,  Fukashi MORISHITA ,  Kenji YOSHINAGA ,  Mihoko AKIYAMA ,  Shinya MIYAZAKI ,  Masakazu ISHIBASHI ,  Katsumi DOSAKA

IPC: G11C15/04

CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US20130182482A1

公开(公告)日：2013-07-18

申请号：US13782892

申请日：2013-03-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Mihoko AKIYAMA

IPC: G11C15/00

CPC classification number: G11C5/14 ,  G11C15/00 ,  G11C15/04

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract translation: 半导体集成电路包括多个输出晶体管，每个输出晶体管根据施加到控制端子的阻抗控制信号所指示的控制值来控制输出电压的大小相对于负载电流的大小;电压监视电路，输出输出 表示输出电压的电压值的电压监视值，以及根据表示输出电压的目标值的基准电压与输出电压监视值之间的误差值的大小来控制控制值的大小的控制电路， 并且基于控制值来控制是否任何这种晶体管进入导通状态。 控制电路根据预先通知负载电流变化的预通知信号，在预定期间内增加控制值相对于误差值的变化步长。

公开(公告)号：US20130249624A1

公开(公告)日：2013-09-26

申请号：US13900210

申请日：2013-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Mihoko AKIYAMA ,  Futoshi IGAUE ,  Kenji YOSHINAGA ,  Masashi MATSUMURA ,  Fukashi MORISHITA

IPC: G05F1/46

CPC classification number: G05F1/468 ,  G11C5/025 ,  G11C5/147

Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US20170060438A1

公开(公告)日：2017-03-02

申请号：US15228631

申请日：2016-08-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Futoshi IGAUE ,  Kenji YOSHINAGA ,  Naoya WATANABE ,  Mihoko AKIYAMA

IPC: G06F3/06 ,  G11C15/04

CPC classification number: G11C15/04

Abstract: The present invention makes it possible to form a circuit configuration that is capable of executing a keyword search at an increased speed while suppressing an increase in the memory capacity of a content-addressable memory. A semiconductor device according to an aspect of the present invention searches an input data string for a predesignated keyword, and includes a first content-addressable memory that stores a partial keyword corresponding to a predetermined number of data beginning with the first data of the keyword, a second content-addressable memory that stores the entirety of the keyword, and a control circuit that is coupled to the first content-addressable memory and to the second content-addressable memory. When a portion matching the partial keyword is detected in the input data string by a search in the first content-addressable memory, the second content-addressable memory executes a search on search data extracted from the input data string.

Abstract translation: 本发明使得可以形成能够以抑制增加内容寻址存储器的存储容量的方式以增加的速度执行关键字搜索的电路配置。 根据本发明的一个方面的半导体器件搜索用于预先指定的关键词的输入数据串，并且包括第一内容寻址存储器，其存储与从关键字的第一数据开始的预定数量的数据相对应的部分关键字， 存储关键字整体的第二可内容寻址存储器，以及耦合到第一可内容寻址存储器和第二内容寻址存储器的控制电路。 当通过在第一可内容寻址存储器中的搜索在输入数据串中检测到匹配部分关键字的部分时，第二内容可寻址存储器对从输入数据串提取的搜索数据执行搜索。

公开(公告)号：US20140313807A1

公开(公告)日：2014-10-23

申请号：US14304349

申请日：2014-06-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Mihoko AKIYAMA

IPC: G11C5/14 ,  G11C15/00

CPC classification number: G11C5/14 ,  G11C15/00 ,  G11C15/04

Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.

Abstract translation: 提供了能够同时追求低功耗和加速的内容可寻址存储装置。 匹配放大器A根据匹配线MLA的电压，确定存储器阵列A的条目中存储在内容可寻址存储器中的搜索数据和数据的一致或非重合。 匹配放大器B根据匹配线MLB的电压确定搜索数据和存储在存储器阵列B的条目中的内容可寻址存储器中的数据的一致或非重合。 块B控制电路指示在存储器阵列A中开始搜索之后的两个周期之后在存储器阵列B中开始搜索。块B激活控制电路指示根据存储器阵列B的电压停止在存储器阵列B中的搜索 在存储器阵列A中搜索后的匹配线MLA。